prev_cmp_ncof.tan.qmsg

quartus2环境中设计的高速任意波形发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_250 register ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_rbh:auto_generated\|pipeline_dffe\[31\] register ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|pipeline_dffe\[20\] 300.03 MHz 3.333 ns Internal " "Info: Clock \"clk_250\" has Internal fmax of 300.03 MHz between source register \"ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_rbh:auto_generated\|pipeline_dffe\[31\]\" and destination register \"ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|pipeline_dffe\[20\]\" (period= 3.333 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.127 ns + Longest register register " "Info: + Longest register to register delay is 3.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_rbh:auto_generated\|pipeline_dffe\[31\] 1 REG LCFF_X42_Y26_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y26_N31; Fanout = 2; REG Node = 'ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_rbh:auto_generated\|pipeline_dffe\[31\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "db/add_sub_rbh.tdf" "" { Text "D:/my_eda/ncof/db/add_sub_rbh.tdf" 33 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.183 ns) + CELL(0.060 ns) 1.243 ns ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|neinyesfmd~31 2 COMB LCCOMB_X37_Y28_N24 1 " "Info: 2: + IC(1.183 ns) + CELL(0.060 ns) = 1.243 ns; Loc. = LCCOMB_X37_Y28_N24; Fanout = 1; COMB Node = 'ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|neinyesfmd~31'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.243 ns" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|neinyesfmd~31 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.346 ns) + CELL(0.426 ns) 3.015 ns ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|op_1~375 3 COMB LCCOMB_X46_Y26_N24 1 " "Info: 3: + IC(1.346 ns) + CELL(0.426 ns) = 3.015 ns; Loc. = LCCOMB_X46_Y26_N24; Fanout = 1; COMB Node = 'ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|op_1~375'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.772 ns" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|neinyesfmd~31 ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|op_1~375 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.112 ns) 3.127 ns ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|pipeline_dffe\[20\] 4 REG LCFF_X46_Y26_N25 1 " "Info: 4: + IC(0.000 ns) + CELL(0.112 ns) = 3.127 ns; Loc. = LCFF_X46_Y26_N25; Fanout = 1; REG Node = 'ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|pipeline_dffe\[20\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.112 ns" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|op_1~375 ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] } "NODE_NAME" } } { "db/add_sub_m4h.tdf" "" { Text "D:/my_eda/ncof/db/add_sub_m4h.tdf" 33 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.598 ns ( 19.12 % ) " "Info: Total cell delay = 0.598 ns ( 19.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.529 ns ( 80.88 % ) " "Info: Total interconnect delay = 2.529 ns ( 80.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.127 ns" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|neinyesfmd~31 ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|op_1~375 ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.127 ns" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|neinyesfmd~31 {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|op_1~375 {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] {} } { 0.000ns 1.183ns 1.346ns 0.000ns } { 0.000ns 0.060ns 0.426ns 0.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.007 ns - Smallest " "Info: - Smallest clock skew is 0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_250 destination 3.394 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_250\" to destination register is 3.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns clk_250 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk_250'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_250 } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.358 ns clk_250~clkctrl 2 COMB CLKCTRL_G3 2232 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.358 ns; Loc. = CLKCTRL_G3; Fanout = 2232; COMB Node = 'clk_250~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_250 clk_250~clkctrl } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.326 ns) + CELL(0.710 ns) 3.394 ns ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|pipeline_dffe\[20\] 3 REG LCFF_X46_Y26_N25 1 " "Info: 3: + IC(1.326 ns) + CELL(0.710 ns) = 3.394 ns; Loc. = LCFF_X46_Y26_N25; Fanout = 1; REG Node = 'ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_dxx:ux002\|lpm_add_sub:ux014\|add_sub_m4h:auto_generated\|pipeline_dffe\[20\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.036 ns" { clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] } "NODE_NAME" } } { "db/add_sub_m4h.tdf" "" { Text "D:/my_eda/ncof/db/add_sub_m4h.tdf" 33 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.674 ns ( 49.32 % ) " "Info: Total cell delay = 1.674 ns ( 49.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.720 ns ( 50.68 % ) " "Info: Total interconnect delay = 1.720 ns ( 50.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.394 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.394 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] {} } { 0.000ns 0.000ns 0.394ns 1.326ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_250 source 3.387 ns - Longest register " "Info: - Longest clock path from clock \"clk_250\" to source register is 3.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns clk_250 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk_250'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_250 } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.358 ns clk_250~clkctrl 2 COMB CLKCTRL_G3 2232 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.358 ns; Loc. = CLKCTRL_G3; Fanout = 2232; COMB Node = 'clk_250~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_250 clk_250~clkctrl } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.319 ns) + CELL(0.710 ns) 3.387 ns ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_rbh:auto_generated\|pipeline_dffe\[31\] 3 REG LCFF_X42_Y26_N31 2 " "Info: 3: + IC(1.319 ns) + CELL(0.710 ns) = 3.387 ns; Loc. = LCFF_X42_Y26_N31; Fanout = 2; REG Node = 'ncofsymbol:inst8\|ncofsymbol_st:ncofsymbol_st_inst\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_rbh:auto_generated\|pipeline_dffe\[31\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.029 ns" { clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "db/add_sub_rbh.tdf" "" { Text "D:/my_eda/ncof/db/add_sub_rbh.tdf" 33 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.674 ns ( 49.42 % ) " "Info: Total cell delay = 1.674 ns ( 49.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.713 ns ( 50.58 % ) " "Info: Total interconnect delay = 1.713 ns ( 50.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.387 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.387 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] {} } { 0.000ns 0.000ns 0.394ns 1.319ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.394 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.394 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] {} } { 0.000ns 0.000ns 0.394ns 1.326ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.387 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.387 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] {} } { 0.000ns 0.000ns 0.394ns 1.319ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" {  } { { "db/add_sub_rbh.tdf" "" { Text "D:/my_eda/ncof/db/add_sub_rbh.tdf" 33 15 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" {  } { { "db/add_sub_m4h.tdf" "" { Text "D:/my_eda/ncof/db/add_sub_m4h.tdf" 33 15 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.127 ns" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|neinyesfmd~31 ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|op_1~375 ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.127 ns" { ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|neinyesfmd~31 {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|op_1~375 {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] {} } { 0.000ns 1.183ns 1.346ns 0.000ns } { 0.000ns 0.060ns 0.426ns 0.112ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.394 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.394 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014|add_sub_m4h:auto_generated|pipeline_dffe[20] {} } { 0.000ns 0.000ns 0.394ns 1.326ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.387 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.387 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_rbh:auto_generated|pipeline_dffe[31] {} } { 0.000ns 0.000ns 0.394ns 1.319ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "altera_internal_jtag~UPDATEUSER register register pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\] pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\] 711.24 MHz Internal " "Info: Clock \"altera_internal_jtag~UPDATEUSER\" Internal fmax is restricted to 711.24 MHz between source register \"pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\]\" and destination register \"pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "703 ps 703 ps 1.406 ns " "Info: fmax restricted to Clock High delay (703 ps) plus Clock Low delay (703 ps) : restricted to 1.406 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.125 ns + Longest register register " "Info: + Longest register to register delay is 1.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\] 1 REG LCFF_X34_Y25_N11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y25_N11; Fanout = 5; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.858 ns) 1.125 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\] 2 REG LCFF_X34_Y25_N23 2 " "Info: 2: + IC(0.267 ns) + CELL(0.858 ns) = 1.125 ns; Loc. = LCFF_X34_Y25_N23; Fanout = 2; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.858 ns ( 76.27 % ) " "Info: Total cell delay = 0.858 ns ( 76.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.267 ns ( 23.73 % ) " "Info: Total interconnect delay = 0.267 ns ( 23.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 0.267ns } { 0.000ns 0.858ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~UPDATEUSER destination 4.986 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~UPDATEUSER\" to destination register is 4.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~UPDATEUSER 1 CLK JTAG_X0_Y26_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X0_Y26_N1; Fanout = 2; CLK Node = 'altera_internal_jtag~UPDATEUSER'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~UPDATEUSER } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.978 ns) + CELL(0.000 ns) 2.978 ns altera_internal_jtag~UPDATEUSERclkctrl 2 COMB CLKCTRL_G11 5 " "Info: 2: + IC(2.978 ns) + CELL(0.000 ns) = 2.978 ns; Loc. = CLKCTRL_G11; Fanout = 5; COMB Node = 'altera_internal_jtag~UPDATEUSERclkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(0.710 ns) 4.986 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\] 3 REG LCFF_X34_Y25_N23 2 " "Info: 3: + IC(1.298 ns) + CELL(0.710 ns) = 4.986 ns; Loc. = LCFF_X34_Y25_N23; Fanout = 2; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.008 ns" { altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.710 ns ( 14.24 % ) " "Info: Total cell delay = 0.710 ns ( 14.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.276 ns ( 85.76 % ) " "Info: Total interconnect delay = 4.276 ns ( 85.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 2.978ns 1.298ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~UPDATEUSER source 4.986 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~UPDATEUSER\" to source register is 4.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~UPDATEUSER 1 CLK JTAG_X0_Y26_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X0_Y26_N1; Fanout = 2; CLK Node = 'altera_internal_jtag~UPDATEUSER'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~UPDATEUSER } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.978 ns) + CELL(0.000 ns) 2.978 ns altera_internal_jtag~UPDATEUSERclkctrl 2 COMB CLKCTRL_G11 5 " "Info: 2: + IC(2.978 ns) + CELL(0.000 ns) = 2.978 ns; Loc. = CLKCTRL_G11; Fanout = 5; COMB Node = 'altera_internal_jtag~UPDATEUSERclkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(0.710 ns) 4.986 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\] 3 REG LCFF_X34_Y25_N11 5 " "Info: 3: + IC(1.298 ns) + CELL(0.710 ns) = 4.986 ns; Loc. = LCFF_X34_Y25_N11; Fanout = 5; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.008 ns" { altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.710 ns ( 14.24 % ) " "Info: Total cell delay = 0.710 ns ( 14.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.276 ns ( 85.76 % ) " "Info: Total interconnect delay = 4.276 ns ( 85.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} } { 0.000ns 2.978ns 1.298ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 2.978ns 1.298ns } { 0.000ns 0.000ns 0.710ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} } { 0.000ns 2.978ns 1.298ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" {  } { { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" {  } { { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 0.267ns } { 0.000ns 0.858ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 2.978ns 1.298ns } { 0.000ns 0.000ns 0.710ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} } { 0.000ns 2.978ns 1.298ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } {  } {  } "" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}