ncof.tan.qmsg

quartus2环境中设计的高速任意波形发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_250 register ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_gar:ux007\|rom_add\[2\] memory ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_lg91:auto_generated\|ram_block1a3~porta_address_reg2 291.29 MHz 3.433 ns Internal " "Info: Clock \"clk_250\" has Internal fmax of 291.29 MHz between source register \"ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_gar:ux007\|rom_add\[2\]\" and destination memory \"ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_lg91:auto_generated\|ram_block1a3~porta_address_reg2\" (period= 3.433 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.138 ns + Longest register memory " "Info: + Longest register to memory delay is 3.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_gar:ux007\|rom_add\[2\] 1 REG LCFF_X38_Y25_N7 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y25_N7; Fanout = 36; REG Node = 'ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_gar:ux007\|rom_add\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] } "NODE_NAME" } } { "../../altera/72/ip/nco/lib/asj_gar.v" "" { Text "D:/altera/72/ip/nco/lib/asj_gar.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.020 ns) + CELL(0.118 ns) 3.138 ns ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_lg91:auto_generated\|ram_block1a3~porta_address_reg2 2 MEM M4K_X39_Y45 1 " "Info: 2: + IC(3.020 ns) + CELL(0.118 ns) = 3.138 ns; Loc. = M4K_X39_Y45; Fanout = 1; MEM Node = 'ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_lg91:auto_generated\|ram_block1a3~porta_address_reg2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.138 ns" { ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_lg91.tdf" "" { Text "D:/my_eda/ncof/db/altsyncram_lg91.tdf" 103 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.118 ns ( 3.76 % ) " "Info: Total cell delay = 0.118 ns ( 3.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.020 ns ( 96.24 % ) " "Info: Total interconnect delay = 3.020 ns ( 96.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.138 ns" { ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.138 ns" { ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 {} } { 0.000ns 3.020ns } { 0.000ns 0.118ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.161 ns - Smallest " "Info: - Smallest clock skew is -0.161 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_250 destination 3.198 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_250\" to destination memory is 3.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns clk_250 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk_250'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_250 } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.358 ns clk_250~clkctrl 2 COMB CLKCTRL_G3 2232 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.358 ns; Loc. = CLKCTRL_G3; Fanout = 2232; COMB Node = 'clk_250~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_250 clk_250~clkctrl } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.287 ns) + CELL(0.553 ns) 3.198 ns ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_lg91:auto_generated\|ram_block1a3~porta_address_reg2 3 MEM M4K_X39_Y45 1 " "Info: 3: + IC(1.287 ns) + CELL(0.553 ns) = 3.198 ns; Loc. = M4K_X39_Y45; Fanout = 1; MEM Node = 'ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_lg91:auto_generated\|ram_block1a3~porta_address_reg2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.840 ns" { clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 } "NODE_NAME" } } { "db/altsyncram_lg91.tdf" "" { Text "D:/my_eda/ncof/db/altsyncram_lg91.tdf" 103 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.517 ns ( 47.44 % ) " "Info: Total cell delay = 1.517 ns ( 47.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.681 ns ( 52.56 % ) " "Info: Total interconnect delay = 1.681 ns ( 52.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.198 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.198 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 {} } { 0.000ns 0.000ns 0.394ns 1.287ns } { 0.000ns 0.964ns 0.000ns 0.553ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_250 source 3.359 ns - Longest register " "Info: - Longest clock path from clock \"clk_250\" to source register is 3.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns clk_250 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk_250'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_250 } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.358 ns clk_250~clkctrl 2 COMB CLKCTRL_G3 2232 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.358 ns; Loc. = CLKCTRL_G3; Fanout = 2232; COMB Node = 'clk_250~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_250 clk_250~clkctrl } "NODE_NAME" } } { "ncof.bdf" "" { Schematic "D:/my_eda/ncof/ncof.bdf" { { 72 -192 -24 88 "clk_250" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.710 ns) 3.359 ns ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_gar:ux007\|rom_add\[2\] 3 REG LCFF_X38_Y25_N7 36 " "Info: 3: + IC(1.291 ns) + CELL(0.710 ns) = 3.359 ns; Loc. = LCFF_X38_Y25_N7; Fanout = 36; REG Node = 'ncofsymbol:inst6\|ncofsymbol_st:ncofsymbol_st_inst\|asj_gar:ux007\|rom_add\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.001 ns" { clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] } "NODE_NAME" } } { "../../altera/72/ip/nco/lib/asj_gar.v" "" { Text "D:/altera/72/ip/nco/lib/asj_gar.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.674 ns ( 49.84 % ) " "Info: Total cell delay = 1.674 ns ( 49.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.685 ns ( 50.16 % ) " "Info: Total interconnect delay = 1.685 ns ( 50.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.359 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.359 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] {} } { 0.000ns 0.000ns 0.394ns 1.291ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.198 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.198 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 {} } { 0.000ns 0.000ns 0.394ns 1.287ns } { 0.000ns 0.964ns 0.000ns 0.553ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.359 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.359 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] {} } { 0.000ns 0.000ns 0.394ns 1.291ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" {  } { { "../../altera/72/ip/nco/lib/asj_gar.v" "" { Text "D:/altera/72/ip/nco/lib/asj_gar.v" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.025 ns + " "Info: + Micro setup delay of destination is 0.025 ns" {  } { { "db/altsyncram_lg91.tdf" "" { Text "D:/my_eda/ncof/db/altsyncram_lg91.tdf" 103 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.138 ns" { ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.138 ns" { ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 {} } { 0.000ns 3.020ns } { 0.000ns 0.118ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.198 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.198 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 {} } { 0.000ns 0.000ns 0.394ns 1.287ns } { 0.000ns 0.964ns 0.000ns 0.553ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.359 ns" { clk_250 clk_250~clkctrl ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.359 ns" { clk_250 {} clk_250~combout {} clk_250~clkctrl {} ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2] {} } { 0.000ns 0.000ns 0.394ns 1.291ns } { 0.000ns 0.964ns 0.000ns 0.710ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "altera_internal_jtag~UPDATEUSER register register pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\] pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\] 711.24 MHz Internal " "Info: Clock \"altera_internal_jtag~UPDATEUSER\" Internal fmax is restricted to 711.24 MHz between source register \"pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\]\" and destination register \"pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "703 ps 703 ps 1.406 ns " "Info: fmax restricted to Clock High delay (703 ps) plus Clock Low delay (703 ps) : restricted to 1.406 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.125 ns + Longest register register " "Info: + Longest register to register delay is 1.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\] 1 REG LCFF_X33_Y34_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y34_N5; Fanout = 5; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.858 ns) 1.125 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\] 2 REG LCFF_X33_Y34_N15 2 " "Info: 2: + IC(0.267 ns) + CELL(0.858 ns) = 1.125 ns; Loc. = LCFF_X33_Y34_N15; Fanout = 2; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.858 ns ( 76.27 % ) " "Info: Total cell delay = 0.858 ns ( 76.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.267 ns ( 23.73 % ) " "Info: Total interconnect delay = 0.267 ns ( 23.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 0.267ns } { 0.000ns 0.858ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~UPDATEUSER destination 5.070 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~UPDATEUSER\" to destination register is 5.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~UPDATEUSER 1 CLK JTAG_X0_Y26_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X0_Y26_N1; Fanout = 2; CLK Node = 'altera_internal_jtag~UPDATEUSER'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~UPDATEUSER } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.070 ns) + CELL(0.000 ns) 3.070 ns altera_internal_jtag~UPDATEUSERclkctrl 2 COMB CLKCTRL_G8 5 " "Info: 2: + IC(3.070 ns) + CELL(0.000 ns) = 3.070 ns; Loc. = CLKCTRL_G8; Fanout = 5; COMB Node = 'altera_internal_jtag~UPDATEUSERclkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.290 ns) + CELL(0.710 ns) 5.070 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\] 3 REG LCFF_X33_Y34_N15 2 " "Info: 3: + IC(1.290 ns) + CELL(0.710 ns) = 5.070 ns; Loc. = LCFF_X33_Y34_N15; Fanout = 2; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.710 ns ( 14.00 % ) " "Info: Total cell delay = 0.710 ns ( 14.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.360 ns ( 86.00 % ) " "Info: Total interconnect delay = 4.360 ns ( 86.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.070 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 3.070ns 1.290ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~UPDATEUSER source 5.070 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~UPDATEUSER\" to source register is 5.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~UPDATEUSER 1 CLK JTAG_X0_Y26_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X0_Y26_N1; Fanout = 2; CLK Node = 'altera_internal_jtag~UPDATEUSER'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~UPDATEUSER } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.070 ns) + CELL(0.000 ns) 3.070 ns altera_internal_jtag~UPDATEUSERclkctrl 2 COMB CLKCTRL_G8 5 " "Info: 2: + IC(3.070 ns) + CELL(0.000 ns) = 3.070 ns; Loc. = CLKCTRL_G8; Fanout = 5; COMB Node = 'altera_internal_jtag~UPDATEUSERclkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.290 ns) + CELL(0.710 ns) 5.070 ns pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\] 3 REG LCFF_X33_Y34_N5 5 " "Info: 3: + IC(1.290 ns) + CELL(0.710 ns) = 5.070 ns; Loc. = LCFF_X33_Y34_N5; Fanout = 5; REG Node = 'pzdyqx:nabboc\|pzdyqx_impl:pzdyqx_impl_inst\|XWDE0671\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.710 ns ( 14.00 % ) " "Info: Total cell delay = 0.710 ns ( 14.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.360 ns ( 86.00 % ) " "Info: Total interconnect delay = 4.360 ns ( 86.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.070 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} } { 0.000ns 3.070ns 1.290ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.070 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 3.070ns 1.290ns } { 0.000ns 0.000ns 0.710ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.070 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} } { 0.000ns 3.070ns 1.290ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" {  } { { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" {  } { { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.125 ns" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 0.267ns } { 0.000ns 0.858ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.070 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } { 0.000ns 3.070ns 1.290ns } { 0.000ns 0.000ns 0.710ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.070 ns" { altera_internal_jtag~UPDATEUSER altera_internal_jtag~UPDATEUSERclkctrl pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.070 ns" { altera_internal_jtag~UPDATEUSER {} altera_internal_jtag~UPDATEUSERclkctrl {} pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] {} } { 0.000ns 3.070ns 1.290ns } { 0.000ns 0.000ns 0.710ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[3] {} } {  } {  } "" } } { "../../altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "D:/altera/72/quartus/libraries/megafunctions/pzdyqx.vhd" 505 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}