mux_kjb.tdf

quartus2环境中设计的高速任意波形发生器

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" LPM_SIZE=2 LPM_WIDTH=9 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 7.2SP3 cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 3 
SUBDESIGN mux_kjb
( 
	data[17..0]	:	input;
	result[8..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w1_n0_mux_dataout	:	WIRE;
	l1_w2_n0_mux_dataout	:	WIRE;
	l1_w3_n0_mux_dataout	:	WIRE;
	l1_w4_n0_mux_dataout	:	WIRE;
	l1_w5_n0_mux_dataout	:	WIRE;
	l1_w6_n0_mux_dataout	:	WIRE;
	l1_w7_n0_mux_dataout	:	WIRE;
	l1_w8_n0_mux_dataout	:	WIRE;
	data_wire[17..0]	: WIRE;
	sel_wire[0..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[1..1];
	l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[2..2];
	l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[3..3];
	l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[4..4];
	l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[5..5];
	l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[6..6];
	l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[16..16] # !(sel_wire[0..0]) & data_wire[7..7];
	l1_w8_n0_mux_dataout = sel_wire[0..0] & data_wire[17..17] # !(sel_wire[0..0]) & data_wire[8..8];
	data_wire[] = ( data[]);
	result[] = ( l1_w8_n0_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n0_mux_dataout);
	sel_wire[] = ( sel[0..0]);
END;
--VALID FILE