ncof.tan.rpt

quartus2环境中设计的高速任意波形发生器

; Report IO Paths Separately                                     ; Off                ;      ;                  ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;                  ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;                  ;             ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_0       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_1       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_2       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_3       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_4       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_5       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_6       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; EPEO2888_7       ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; lcell:LJMV0916_0 ; MDCK2395    ;
; Cut Timing Path                                                ; On                 ;      ; lcell:WCRO7487_0 ; MDCK2395    ;
+----------------------------------------------------------------+--------------------+------+------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                             ;
+---------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name                 ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+---------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_250                         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~UPDATEUSER ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP    ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~CLKDRUSER  ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+---------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_250'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                    ; To                                                                                                                                                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 291.29 MHz ( period = 3.433 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2   ; clk_250    ; clk_250  ; None                        ; None                      ; 3.138 ns                ;
; N/A                                     ; 292.83 MHz ( period = 3.415 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0|altsyncram_gg91:auto_generated|ram_block1a1~porta_address_reg2   ; clk_250    ; clk_250  ; None                        ; None                      ; 3.125 ns                ;
; N/A                                     ; 294.90 MHz ( period = 3.391 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a0~porta_address_reg2   ; clk_250    ; clk_250  ; None                        ; None                      ; 3.107 ns                ;
; N/A                                     ; 297.97 MHz ( period = 3.356 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a4~porta_address_reg2   ; clk_250    ; clk_250  ; None                        ; None                      ; 3.076 ns                ;
; N/A                                     ; 302.21 MHz ( period = 3.309 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[0]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a2~porta_address_reg0   ; clk_250    ; clk_250  ; None                        ; None                      ; 3.013 ns                ;
; N/A                                     ; 308.45 MHz ( period = 3.242 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[1]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a2~porta_address_reg1   ; clk_250    ; clk_250  ; None                        ; None                      ; 2.946 ns                ;
; N/A                                     ; 311.33 MHz ( period = 3.212 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[4]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a0~porta_address_reg4   ; clk_250    ; clk_250  ; None                        ; None                      ; 2.908 ns                ;
; N/A                                     ; 312.79 MHz ( period = 3.197 ns )                    ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[4]                                                                              ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg4   ; clk_250    ; clk_250  ; None                        ; None                      ; 2.882 ns                ;