ncof.tan.rpt

quartus2环境中设计的高速任意波形发生器

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+------------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+
; Type                                           ; Slack ; Required Time ; Actual Time                                    ; From                                                                               ; To                                                                                                                                                                        ; From Clock                      ; To Clock                        ; Failed Paths ;
+------------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+
; Worst-case tsu                                 ; N/A   ; None          ; 8.543 ns                                       ; resetn                                                                             ; ncofsymbol:inst7|ncofsymbol_st:ncofsymbol_st_inst|asj_altqmcpipe:ux000|phi_int_arr_reg[15]                                                                                ; --                              ; clk_250                         ; 0            ;
; Worst-case tco                                 ; N/A   ; None          ; 9.559 ns                                       ; ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_mob_rw:ux122|data_out[6] ; fsin_o7[6]                                                                                                                                                                ; clk_250                         ; --                              ; 0            ;
; Worst-case tpd                                 ; N/A   ; None          ; 2.217 ns                                       ; altera_internal_jtag~TDO                                                           ; altera_reserved_tdo                                                                                                                                                       ; --                              ; --                              ; 0            ;
; Worst-case th                                  ; N/A   ; None          ; 1.369 ns                                       ; altera_internal_jtag~TDIUTAP                                                       ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|DJFL8584[3]                                                                                                  ; --                              ; altera_internal_jtag~CLKDRUSER  ; 0            ;
; Clock Setup: 'clk_250'                         ; N/A   ; None          ; 291.29 MHz ( period = 3.433 ns )               ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007|rom_add[2]         ; ncofsymbol:inst6|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_lg91:auto_generated|ram_block1a3~porta_address_reg2 ; clk_250                         ; clk_250                         ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'    ; N/A   ; None          ; 328.95 MHz ( period = 3.040 ns )               ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                          ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                                          ; altera_internal_jtag~TCKUTAP    ; altera_internal_jtag~TCKUTAP    ; 0            ;
; Clock Setup: 'altera_internal_jtag~CLKDRUSER'  ; N/A   ; None          ; 574.05 MHz ( period = 1.742 ns )               ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0]           ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4]                                                                                                  ; altera_internal_jtag~CLKDRUSER  ; altera_internal_jtag~CLKDRUSER  ; 0            ;
; Clock Setup: 'altera_internal_jtag~UPDATEUSER' ; N/A   ; None          ; Restricted to 711.24 MHz ( period = 1.406 ns ) ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2]                             ; pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[1]                                                                                                                    ; altera_internal_jtag~UPDATEUSER ; altera_internal_jtag~UPDATEUSER ; 0            ;
; Total number of failed paths                   ;       ;               ;                                                ;                                                                                    ;                                                                                                                                                                           ;                                 ;                                 ; 0            ;
+------------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                    ;
+----------------------------------------------------------------+--------------------+------+------------------+-------------+
; Option                                                         ; Setting            ; From ; To               ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+------------------+-------------+
; Device Name                                                    ; EP2S60F672I4       ;      ;                  ;             ;
; Timing Models                                                  ; Final              ;      ;                  ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;                  ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;                  ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;                  ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;                  ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;                  ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;                  ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;                  ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;                  ;             ;
; Enable Clock Latency                                           ; Off                ;      ;                  ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;                  ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;                  ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;                  ;             ;
; Number of paths to report                                      ; 200                ;      ;                  ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;                  ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;                  ;             ;