ncof.vhd

quartus2环境中设计的高速任意波形发生器

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY ncof IS 
	port
	(
		clk_250 :  IN  STD_LOGIC;
		resetn :  IN  STD_LOGIC;
		clk_en :  IN  STD_LOGIC;
		phase_mod_i :  IN  STD_LOGIC_VECTOR(15 downto 0);
		phase_mod_i2 :  IN  STD_LOGIC_VECTOR(15 downto 0);
		phase_mod_i6 :  IN  STD_LOGIC_VECTOR(15 downto 0);
		phi_inc_i :  IN  STD_LOGIC_VECTOR(31 downto 0);
		phi_inc_i1 :  IN  STD_LOGIC_VECTOR(31 downto 0);
		phi_inc_i5 :  IN  STD_LOGIC_VECTOR(31 downto 0);
		out_valid :  OUT  STD_LOGIC;
		out_valid4 :  OUT  STD_LOGIC;
		out_valid8 :  OUT  STD_LOGIC;
		fsin_o :  OUT  STD_LOGIC_VECTOR(9 downto 0);
		fsin_o3 :  OUT  STD_LOGIC_VECTOR(9 downto 0);
		fsin_o7 :  OUT  STD_LOGIC_VECTOR(9 downto 0)
	);
END ncof;

ARCHITECTURE bdf_type OF ncof IS 

component ncofsymbol
	PORT(clk : IN STD_LOGIC;
		 reset_n : IN STD_LOGIC;
		 clken : IN STD_LOGIC;
		 phase_mod_i : IN STD_LOGIC_VECTOR(15 downto 0);
		 phi_inc_i : IN STD_LOGIC_VECTOR(31 downto 0);
		 out_valid : OUT STD_LOGIC;
		 fsin_o : OUT STD_LOGIC_VECTOR(9 downto 0)
	);
end component;



BEGIN 



b2v_inst6 : ncofsymbol
PORT MAP(clk => clk_250,
		 reset_n => resetn,
		 clken => clk_en,
		 phase_mod_i => phase_mod_i,
		 phi_inc_i => phi_inc_i,
		 out_valid => out_valid,
		 fsin_o => fsin_o);

b2v_inst7 : ncofsymbol
PORT MAP(clk => clk_250,
		 reset_n => resetn,
		 clken => clk_en,
		 phase_mod_i => phase_mod_i2,
		 phi_inc_i => phi_inc_i1,
		 out_valid => out_valid4,
		 fsin_o => fsin_o3);

b2v_inst8 : ncofsymbol
PORT MAP(clk => clk_250,
		 reset_n => resetn,
		 clken => clk_en,
		 phase_mod_i => phase_mod_i6,
		 phi_inc_i => phi_inc_i5,
		 out_valid => out_valid8,
		 fsin_o => fsin_o7);

END;