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📄 ncof.map.rpt

📁 quartus2环境中设计的高速任意波形发生器
💻 RPT
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 74. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_dxx:ux002|lpm_add_sub:ux014
 75. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_apr_dxx:ux0219
 76. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_pxx:ux004
 77. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_pxx:ux004|lpm_add_sub:acc
 78. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_gar:ux007
 79. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|sid_2c_1p:sid2c
 80. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120
 81. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0
 82. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0121
 83. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_as_m_cen:ux0121|altsyncram:altsyncram_component0
 84. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|segment_sel_sgl:rot
 85. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_mob_rw:ux122
 86. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_isdr:ux710isdr
 87. Parameter Settings for User Entity Instance: ncofsymbol:inst8|ncofsymbol_st:ncofsymbol_st_inst|asj_nco_isdr:ux710isdr|lpm_counter:lpm_counter_component
 88. Parameter Settings for Inferred Entity Instance: pzdyqx:nabboc
 89. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 90. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status   ; Successful - Sat May 02 09:48:55 2009         ;
; Quartus II Version            ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name                 ; ncof                                          ;
; Top-level Entity Name         ; ncof                                          ;
; Family                        ; Stratix II                                    ;
; Logic utilization             ; N/A                                           ;
;     Combinational ALUTs       ; 688                                           ;
;     Dedicated logic registers ; 967                                           ;
; Total registers               ; 967                                           ;
; Total pins                    ; 185                                           ;
; Total virtual pins            ; 0                                             ;
; Total block memory bits       ; 442,368                                       ;
; DSP block 9-bit elements      ; 0                                             ;
; Total PLLs                    ; 0                                             ;
; Total DLLs                    ; 0                                             ;
+-------------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                         ;
+-----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                      ; Setting            ; Default Value      ;
+-----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                      ; EP2S60F672I4       ;                    ;
; Top-level entity name                                                       ; ncof               ; ncof               ;
; Family name                                                                 ; Stratix II         ; Stratix II         ;
; Use Generated Physical Constraints File                                     ; Off                ;                    ;
; Use smart compilation                                                       ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                         ; 1                  ; 1                  ;
; Restructure Multiplexers                                                    ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                         ; Off                ; Off                ;
; Preserve fewer node names                                                   ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                   ; Off                ; Off                ;
; Verilog Version                                                             ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                    ; Auto               ; Auto               ;
; Safe State Machine                                                          ; Off                ; Off                ;
; Extract Verilog State Machines                                              ; On                 ; On                 ;
; Extract VHDL State Machines                                                 ; On                 ; On                 ;

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