t_ncof.vhd

quartus2环境中设计的高速任意波形发生器

END PROCESS t_prcs_out_valid;

-- expected out_valid4
t_prcs_out_valid4: PROCESS
BEGIN
	out_valid4_expected <= 'X';
WAIT;
END PROCESS t_prcs_out_valid4;

-- expected out_valid8
t_prcs_out_valid8: PROCESS
BEGIN
	out_valid8_expected <= 'X';
WAIT;
END PROCESS t_prcs_out_valid8;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(fsin_o_expected,fsin_o3_expected,fsin_o7_expected,out_valid_expected,out_valid4_expected,out_valid8_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(fsin_o,fsin_o3,fsin_o7,out_valid,out_valid4,out_valid8)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_fsin_o_exp : STD_LOGIC_VECTOR(9 DOWNTO 0) := "UUUUUUUUUU";
VARIABLE last_fsin_o3_exp : STD_LOGIC_VECTOR(9 DOWNTO 0) := "UUUUUUUUUU";
VARIABLE last_fsin_o7_exp : STD_LOGIC_VECTOR(9 DOWNTO 0) := "UUUUUUUUUU";
VARIABLE last_out_valid_exp : STD_LOGIC := 'U';
VARIABLE last_out_valid4_exp : STD_LOGIC := 'U';
VARIABLE last_out_valid8_exp : STD_LOGIC := 'U';

VARIABLE on_first_change : trackvec := "111111";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,fsin_o_name);write(txt,string'(" = "));write(txt,fsin_o_expected_prev);
	write(txt,string'("| expected "));write(txt,fsin_o3_name);write(txt,string'(" = "));write(txt,fsin_o3_expected_prev);
	write(txt,string'("| expected "));write(txt,fsin_o7_name);write(txt,string'(" = "));write(txt,fsin_o7_expected_prev);
	write(txt,string'("| expected "));write(txt,out_valid_name);write(txt,string'(" = "));write(txt,out_valid_expected_prev);
	write(txt,string'("| expected "));write(txt,out_valid4_name);write(txt,string'(" = "));write(txt,out_valid4_expected_prev);
	write(txt,string'("| expected "));write(txt,out_valid8_name);write(txt,string'(" = "));write(txt,out_valid8_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,fsin_o_name);write(txt,string'(" = "));write(txt,fsin_o_prev);
	write(txt,string'("| real "));write(txt,fsin_o3_name);write(txt,string'(" = "));write(txt,fsin_o3_prev);
	write(txt,string'("| real "));write(txt,fsin_o7_name);write(txt,string'(" = "));write(txt,fsin_o7_prev);
	write(txt,string'("| real "));write(txt,out_valid_name);write(txt,string'(" = "));write(txt,out_valid_prev);
	write(txt,string'("| real "));write(txt,out_valid4_name);write(txt,string'(" = "));write(txt,out_valid4_prev);
	write(txt,string'("| real "));write(txt,out_valid8_name);write(txt,string'(" = "));write(txt,out_valid8_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( fsin_o_expected_prev /= "XXXXXXXXXX" ) AND (fsin_o_expected_prev /= "UUUUUUUUUU" ) AND (fsin_o_prev /= fsin_o_expected_prev) AND (
	(fsin_o_expected_prev /= last_fsin_o_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("fsin_o",fsin_o_expected_prev,fsin_o_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_fsin_o_exp := fsin_o_expected_prev;
END IF;
IF ( fsin_o3_expected_prev /= "XXXXXXXXXX" ) AND (fsin_o3_expected_prev /= "UUUUUUUUUU" ) AND (fsin_o3_prev /= fsin_o3_expected_prev) AND (
	(fsin_o3_expected_prev /= last_fsin_o3_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("fsin_o3",fsin_o3_expected_prev,fsin_o3_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_fsin_o3_exp := fsin_o3_expected_prev;
END IF;
IF ( fsin_o7_expected_prev /= "XXXXXXXXXX" ) AND (fsin_o7_expected_prev /= "UUUUUUUUUU" ) AND (fsin_o7_prev /= fsin_o7_expected_prev) AND (
	(fsin_o7_expected_prev /= last_fsin_o7_exp) OR
	(on_first_change(3) = '1')
		) THEN
	throw_error("fsin_o7",fsin_o7_expected_prev,fsin_o7_prev);
	num_mismatches(2) <= num_mismatches(2) + 1;
	on_first_change(3) := '0';
	last_fsin_o7_exp := fsin_o7_expected_prev;
END IF;
IF ( out_valid_expected_prev /= 'X' ) AND (out_valid_expected_prev /= 'U' ) AND (out_valid_prev /= out_valid_expected_prev) AND (
	(out_valid_expected_prev /= last_out_valid_exp) OR
	(on_first_change(4) = '1')
		) THEN
	throw_error("out_valid",out_valid_expected_prev,out_valid_prev);
	num_mismatches(3) <= num_mismatches(3) + 1;
	on_first_change(4) := '0';
	last_out_valid_exp := out_valid_expected_prev;
END IF;
IF ( out_valid4_expected_prev /= 'X' ) AND (out_valid4_expected_prev /= 'U' ) AND (out_valid4_prev /= out_valid4_expected_prev) AND (
	(out_valid4_expected_prev /= last_out_valid4_exp) OR
	(on_first_change(5) = '1')
		) THEN
	throw_error("out_valid4",out_valid4_expected_prev,out_valid4_prev);
	num_mismatches(4) <= num_mismatches(4) + 1;
	on_first_change(5) := '0';
	last_out_valid4_exp := out_valid4_expected_prev;
END IF;
IF ( out_valid8_expected_prev /= 'X' ) AND (out_valid8_expected_prev /= 'U' ) AND (out_valid8_prev /= out_valid8_expected_prev) AND (
	(out_valid8_expected_prev /= last_out_valid8_exp) OR
	(on_first_change(6) = '1')
		) THEN
	throw_error("out_valid8",out_valid8_expected_prev,out_valid8_prev);
	num_mismatches(5) <= num_mismatches(5) + 1;
	on_first_change(6) := '0';
	last_out_valid8_exp := out_valid8_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1) + num_mismatches(2) + num_mismatches(3) + num_mismatches(4) + num_mismatches(5);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.ncof_vhd_tb_types.ALL;                                         

ENTITY ncof_vhd_vec_tst IS
END ncof_vhd_vec_tst;
ARCHITECTURE ncof_arch OF ncof_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL clk_250 : STD_LOGIC;
SIGNAL clk_en : STD_LOGIC;
SIGNAL fsin_o : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL fsin_o3 : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL fsin_o7 : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL out_valid : STD_LOGIC;
SIGNAL out_valid4 : STD_LOGIC;
SIGNAL out_valid8 : STD_LOGIC;
SIGNAL phase_mod_i : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL phase_mod_i2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL phase_mod_i6 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL phi_inc_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL phi_inc_i1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL phi_inc_i5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL resetn : STD_LOGIC;
SIGNAL sampler : sample_type;

COMPONENT ncof
	PORT (
	clk_250 : IN STD_LOGIC;
	clk_en : IN STD_LOGIC;
	fsin_o : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
	fsin_o3 : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
	fsin_o7 : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
	out_valid : OUT STD_LOGIC;
	out_valid4 : OUT STD_LOGIC;
	out_valid8 : OUT STD_LOGIC;
	phase_mod_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	phase_mod_i2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	phase_mod_i6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	phi_inc_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	phi_inc_i1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	phi_inc_i5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	resetn : IN STD_LOGIC
	);
END COMPONENT;
COMPONENT ncof_vhd_check_tst
PORT (
	fsin_o : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	fsin_o3 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	fsin_o7 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	out_valid : IN STD_LOGIC;
	out_valid4 : IN STD_LOGIC;
	out_valid8 : IN STD_LOGIC;
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT ncof_vhd_sample_tst
PORT (
	clk_250 : IN STD_LOGIC;
	clk_en : IN STD_LOGIC;
	phase_mod_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	phase_mod_i2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	phase_mod_i6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	phi_inc_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	phi_inc_i1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	phi_inc_i5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	resetn : IN STD_LOGIC;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : ncof
	PORT MAP (
-- list connections between master ports and signals
	clk_250 => clk_250,
	clk_en => clk_en,
	fsin_o => fsin_o,
	fsin_o3 => fsin_o3,
	fsin_o7 => fsin_o7,
	out_valid => out_valid,
	out_valid4 => out_valid4,
	out_valid8 => out_valid8,
	phase_mod_i => phase_mod_i,
	phase_mod_i2 => phase_mod_i2,
	phase_mod_i6 => phase_mod_i6,
	phi_inc_i => phi_inc_i,
	phi_inc_i1 => phi_inc_i1,
	phi_inc_i5 => phi_inc_i5,
	resetn => resetn
	);

-- clk_250
t_prcs_clk_250: PROCESS
BEGIN
LOOP
	clk_250 <= '0';
	WAIT FOR 2000 ps;
	clk_250 <= '1';
	WAIT FOR 2000 ps;
	IF (NOW >= 1000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_clk_250;

-- clk_en
t_prcs_clk_en: PROCESS
BEGIN
	clk_en <= '1';
WAIT;
END PROCESS t_prcs_clk_en;
-- phase_mod_i[15]
t_prcs_phase_mod_i_15: PROCESS
BEGIN
	phase_mod_i(15) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_15;
-- phase_mod_i[14]
t_prcs_phase_mod_i_14: PROCESS
BEGIN
	phase_mod_i(14) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_14;
-- phase_mod_i[13]
t_prcs_phase_mod_i_13: PROCESS
BEGIN
	phase_mod_i(13) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_13;
-- phase_mod_i[12]
t_prcs_phase_mod_i_12: PROCESS
BEGIN
	phase_mod_i(12) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_12;
-- phase_mod_i[11]
t_prcs_phase_mod_i_11: PROCESS
BEGIN
	phase_mod_i(11) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_11;
-- phase_mod_i[10]
t_prcs_phase_mod_i_10: PROCESS
BEGIN
	phase_mod_i(10) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_10;
-- phase_mod_i[9]
t_prcs_phase_mod_i_9: PROCESS
BEGIN
	phase_mod_i(9) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_9;
-- phase_mod_i[8]
t_prcs_phase_mod_i_8: PROCESS
BEGIN
	phase_mod_i(8) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_8;
-- phase_mod_i[7]
t_prcs_phase_mod_i_7: PROCESS
BEGIN
	phase_mod_i(7) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_7;
-- phase_mod_i[6]
t_prcs_phase_mod_i_6: PROCESS
BEGIN
	phase_mod_i(6) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_6;
-- phase_mod_i[5]
t_prcs_phase_mod_i_5: PROCESS
BEGIN
	phase_mod_i(5) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_5;
-- phase_mod_i[4]
t_prcs_phase_mod_i_4: PROCESS
BEGIN
	phase_mod_i(4) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_4;
-- phase_mod_i[3]
t_prcs_phase_mod_i_3: PROCESS
BEGIN
	phase_mod_i(3) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_3;
-- phase_mod_i[2]
t_prcs_phase_mod_i_2: PROCESS
BEGIN
	phase_mod_i(2) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_2;
-- phase_mod_i[1]
t_prcs_phase_mod_i_1: PROCESS
BEGIN
	phase_mod_i(1) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_1;
-- phase_mod_i[0]
t_prcs_phase_mod_i_0: PROCESS
BEGIN
	phase_mod_i(0) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i_0;
-- phase_mod_i2[15]
t_prcs_phase_mod_i2_15: PROCESS
BEGIN
	phase_mod_i2(15) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_15;
-- phase_mod_i2[14]
t_prcs_phase_mod_i2_14: PROCESS
BEGIN
	phase_mod_i2(14) <= '1';
WAIT;
END PROCESS t_prcs_phase_mod_i2_14;
-- phase_mod_i2[13]
t_prcs_phase_mod_i2_13: PROCESS
BEGIN
	phase_mod_i2(13) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_13;
-- phase_mod_i2[12]
t_prcs_phase_mod_i2_12: PROCESS
BEGIN
	phase_mod_i2(12) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_12;
-- phase_mod_i2[11]
t_prcs_phase_mod_i2_11: PROCESS
BEGIN
	phase_mod_i2(11) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_11;
-- phase_mod_i2[10]
t_prcs_phase_mod_i2_10: PROCESS
BEGIN
	phase_mod_i2(10) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_10;
-- phase_mod_i2[9]
t_prcs_phase_mod_i2_9: PROCESS
BEGIN
	phase_mod_i2(9) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_9;
-- phase_mod_i2[8]
t_prcs_phase_mod_i2_8: PROCESS
BEGIN
	phase_mod_i2(8) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_8;
-- phase_mod_i2[7]
t_prcs_phase_mod_i2_7: PROCESS
BEGIN
	phase_mod_i2(7) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_7;
-- phase_mod_i2[6]
t_prcs_phase_mod_i2_6: PROCESS
BEGIN
	phase_mod_i2(6) <= '0';
WAIT;
END PROCESS t_prcs_phase_mod_i2_6;
-- phase_mod_i2[5]
t_prcs_phase_mod_i2_5: PROCESS