📄 t_ncof.vhd
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "05/02/2009 15:18:07"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : ncof
--
-- Simulation tool : 3rd Party
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE ncof_vhd_tb_types IS
-- input port types
-- output port names
CONSTANT fsin_o_name : STRING (1 TO 6) := "fsin_o";
CONSTANT fsin_o3_name : STRING (1 TO 7) := "fsin_o3";
CONSTANT fsin_o7_name : STRING (1 TO 7) := "fsin_o7";
CONSTANT out_valid_name : STRING (1 TO 9) := "out_valid";
CONSTANT out_valid4_name : STRING (1 TO 10) := "out_valid4";
CONSTANT out_valid8_name : STRING (1 TO 10) := "out_valid8";
-- n(outputs)
CONSTANT o_num : INTEGER := 6;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END ncof_vhd_tb_types;
PACKAGE BODY ncof_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END ncof_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.ncof_vhd_tb_types.ALL;
ENTITY ncof_vhd_sample_tst IS
PORT (
clk_250 : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
phase_mod_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
phase_mod_i2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
phase_mod_i6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
phi_inc_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
phi_inc_i1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
phi_inc_i5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
resetn : IN STD_LOGIC;
sampler : OUT sample_type
);
END ncof_vhd_sample_tst;
ARCHITECTURE sample_arch OF ncof_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '1';
BEGIN
t_prcs_sample : PROCESS ( clk_250 , clk_en , phase_mod_i , phase_mod_i2 , phase_mod_i6 , phi_inc_i , phi_inc_i1 , phi_inc_i5 , resetn )
BEGIN
IF (NOW > 0 ps) AND (NOW < 1000000 ps) THEN
tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.ncof_vhd_tb_types.ALL;
ENTITY ncof_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
fsin_o : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
fsin_o3 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
fsin_o7 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
out_valid : IN STD_LOGIC;
out_valid4 : IN STD_LOGIC;
out_valid8 : IN STD_LOGIC;
sampler : IN sample_type
);
END ncof_vhd_check_tst;
ARCHITECTURE ovec_arch OF ncof_vhd_check_tst IS
SIGNAL fsin_o_expected,fsin_o_expected_prev,fsin_o_prev : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL fsin_o3_expected,fsin_o3_expected_prev,fsin_o3_prev : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL fsin_o7_expected,fsin_o7_expected_prev,fsin_o7_prev : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL out_valid_expected,out_valid_expected_prev,out_valid_prev : STD_LOGIC;
SIGNAL out_valid4_expected,out_valid4_expected_prev,out_valid4_prev : STD_LOGIC;
SIGNAL out_valid8_expected,out_valid8_expected_prev,out_valid8_prev : STD_LOGIC;
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
fsin_o_expected_prev <= fsin_o_expected;
fsin_o3_expected_prev <= fsin_o3_expected;
fsin_o7_expected_prev <= fsin_o7_expected;
out_valid_expected_prev <= out_valid_expected;
out_valid4_expected_prev <= out_valid4_expected;
out_valid8_expected_prev <= out_valid8_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
fsin_o_prev <= fsin_o;
fsin_o3_prev <= fsin_o3;
fsin_o7_prev <= fsin_o7;
out_valid_prev <= out_valid;
out_valid4_prev <= out_valid4;
out_valid8_prev <= out_valid8;
END PROCESS t_prcs_update_o_real_hist;
-- expected fsin_o[9]
t_prcs_fsin_o_9: PROCESS
BEGIN
fsin_o_expected(9) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_9;
-- expected fsin_o[8]
t_prcs_fsin_o_8: PROCESS
BEGIN
fsin_o_expected(8) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_8;
-- expected fsin_o[7]
t_prcs_fsin_o_7: PROCESS
BEGIN
fsin_o_expected(7) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_7;
-- expected fsin_o[6]
t_prcs_fsin_o_6: PROCESS
BEGIN
fsin_o_expected(6) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_6;
-- expected fsin_o[5]
t_prcs_fsin_o_5: PROCESS
BEGIN
fsin_o_expected(5) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_5;
-- expected fsin_o[4]
t_prcs_fsin_o_4: PROCESS
BEGIN
fsin_o_expected(4) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_4;
-- expected fsin_o[3]
t_prcs_fsin_o_3: PROCESS
BEGIN
fsin_o_expected(3) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_3;
-- expected fsin_o[2]
t_prcs_fsin_o_2: PROCESS
BEGIN
fsin_o_expected(2) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_2;
-- expected fsin_o[1]
t_prcs_fsin_o_1: PROCESS
BEGIN
fsin_o_expected(1) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_1;
-- expected fsin_o[0]
t_prcs_fsin_o_0: PROCESS
BEGIN
fsin_o_expected(0) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o_0;
-- expected fsin_o3[9]
t_prcs_fsin_o3_9: PROCESS
BEGIN
fsin_o3_expected(9) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_9;
-- expected fsin_o3[8]
t_prcs_fsin_o3_8: PROCESS
BEGIN
fsin_o3_expected(8) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_8;
-- expected fsin_o3[7]
t_prcs_fsin_o3_7: PROCESS
BEGIN
fsin_o3_expected(7) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_7;
-- expected fsin_o3[6]
t_prcs_fsin_o3_6: PROCESS
BEGIN
fsin_o3_expected(6) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_6;
-- expected fsin_o3[5]
t_prcs_fsin_o3_5: PROCESS
BEGIN
fsin_o3_expected(5) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_5;
-- expected fsin_o3[4]
t_prcs_fsin_o3_4: PROCESS
BEGIN
fsin_o3_expected(4) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_4;
-- expected fsin_o3[3]
t_prcs_fsin_o3_3: PROCESS
BEGIN
fsin_o3_expected(3) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_3;
-- expected fsin_o3[2]
t_prcs_fsin_o3_2: PROCESS
BEGIN
fsin_o3_expected(2) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_2;
-- expected fsin_o3[1]
t_prcs_fsin_o3_1: PROCESS
BEGIN
fsin_o3_expected(1) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_1;
-- expected fsin_o3[0]
t_prcs_fsin_o3_0: PROCESS
BEGIN
fsin_o3_expected(0) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o3_0;
-- expected fsin_o7[9]
t_prcs_fsin_o7_9: PROCESS
BEGIN
fsin_o7_expected(9) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_9;
-- expected fsin_o7[8]
t_prcs_fsin_o7_8: PROCESS
BEGIN
fsin_o7_expected(8) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_8;
-- expected fsin_o7[7]
t_prcs_fsin_o7_7: PROCESS
BEGIN
fsin_o7_expected(7) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_7;
-- expected fsin_o7[6]
t_prcs_fsin_o7_6: PROCESS
BEGIN
fsin_o7_expected(6) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_6;
-- expected fsin_o7[5]
t_prcs_fsin_o7_5: PROCESS
BEGIN
fsin_o7_expected(5) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_5;
-- expected fsin_o7[4]
t_prcs_fsin_o7_4: PROCESS
BEGIN
fsin_o7_expected(4) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_4;
-- expected fsin_o7[3]
t_prcs_fsin_o7_3: PROCESS
BEGIN
fsin_o7_expected(3) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_3;
-- expected fsin_o7[2]
t_prcs_fsin_o7_2: PROCESS
BEGIN
fsin_o7_expected(2) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_2;
-- expected fsin_o7[1]
t_prcs_fsin_o7_1: PROCESS
BEGIN
fsin_o7_expected(1) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_1;
-- expected fsin_o7[0]
t_prcs_fsin_o7_0: PROCESS
BEGIN
fsin_o7_expected(0) <= 'X';
WAIT;
END PROCESS t_prcs_fsin_o7_0;
-- expected out_valid
t_prcs_out_valid: PROCESS
BEGIN
out_valid_expected <= 'X';
WAIT;
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