22.txt

来自「使用VHDL实现16进制的计数器的算法程序」· 文本 代码 · 共 81 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cpu IS
	PORT
	(
	 ALE,RESET,CLK		: IN	STD_LOGIC;
		RA,M,WD				: IN	STD_LOGIC_VECTOR(1 DOWNTO 0);
		D:IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
		
		PCL,PCH	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END cpu;
ARCHITECTURE one OF cpu IS
	SIGNAL Y0,Y1,Y2,Y3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL PC1,PC2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL PC : STD_LOGIC_VECTOR(15 DOWNTO 0);
	
BEGIN
PROCESS( CLK,RESET,RA,M,ALE,WD,D,Y0,Y1,Y2,Y3,PC1,PC2,PC)
BEGIN
 
	
	IF(CLK'EVENT AND CLK = '0' AND ALE='1' AND RESET='1') THEN
	IF (M="00") THEN
	PC1<=D;
	PC(7 DOWNTO 0)<=D;
	
	ELSIF(M="01") THEN
	PC2<=D;
	PC(15 DOWNTO 8)<=D;
	
	ELSIF(M="10") THEN
	PC<=PC+1;
	
	ELSIF(M="11") THEN
	PC<=PC-1;
	END IF;
	END IF;
	pc1<=pc(7 downto 0);
	pc2<=pc( 15 downto 8);
	PCL<=PC1;
	PCH<=PC2;
	
	IF(RESET='0' AND ALE='1')THEN
	PCL<="00000000";
	PCH<="00000000";
	END IF;
	
	IF(RA="00") THEN
	IF(WD="01")THEN
	Y0<=D;
	 ELSIF(WD="10" AND ALE='0')  THEN
	 PCL<=Y0;
	END IF;
	
	ELSIF(RA="01") THEN
	IF(WD="01")THEN
	Y1<=D;
	 ELSIF(WD="10" AND ALE='0')  THEN
	 PCL<=Y1;
	END IF;
	
	 ELSIF(RA="10") THEN
	IF(WD="01")THEN
	Y2<=D;
	 ELSIF(WD="10" AND ALE='0')  THEN
	 PCL<=Y2;
	END IF;
	
	 ELSIF(RA="11") THEN
	IF(WD="01") THEN
	Y3<=D;
	 ELSIF(WD="10" AND ALE='0')  THEN
	 PCL<=Y3;
	END IF;
	END IF;

	END PROCESS;
	END one;