main.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "SW2 register register alarmclock:inst11\|hour_set1\[1\] alarmclock:inst11\|hour_set0\[2\] 405.19 MHz Internal " "Info: Clock \"SW2\" Internal fmax is restricted to 405.19 MHz between source register \"alarmclock:inst11\|hour_set1\[1\]\" and destination register \"alarmclock:inst11\|hour_set0\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.102 ns + Longest register register " "Info: + Longest register to register delay is 2.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarmclock:inst11\|hour_set1\[1\] 1 REG LC_X20_Y5_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y5_N6; Fanout = 5; REG Node = 'alarmclock:inst11\|hour_set1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { alarmclock:inst11|hour_set1[1] } "NODE_NAME" } } { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.454 ns) 0.907 ns alarmclock:inst11\|hour_set0\[0\]~530 2 COMB LC_X20_Y5_N9 2 " "Info: 2: + IC(0.453 ns) + CELL(0.454 ns) = 0.907 ns; Loc. = LC_X20_Y5_N9; Fanout = 2; COMB Node = 'alarmclock:inst11\|hour_set0\[0\]~530'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.907 ns" { alarmclock:inst11|hour_set1[1] alarmclock:inst11|hour_set0[0]~530 } "NODE_NAME" } } { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.225 ns) 1.486 ns alarmclock:inst11\|hour_set0\[0\]~532 3 COMB LC_X20_Y5_N3 3 " "Info: 3: + IC(0.354 ns) + CELL(0.225 ns) = 1.486 ns; Loc. = LC_X20_Y5_N3; Fanout = 3; COMB Node = 'alarmclock:inst11\|hour_set0\[0\]~532'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.579 ns" { alarmclock:inst11|hour_set0[0]~530 alarmclock:inst11|hour_set0[0]~532 } "NODE_NAME" } } { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.238 ns) 2.102 ns alarmclock:inst11\|hour_set0\[2\] 4 REG LC_X20_Y5_N5 6 " "Info: 4: + IC(0.378 ns) + CELL(0.238 ns) = 2.102 ns; Loc. = LC_X20_Y5_N5; Fanout = 6; REG Node = 'alarmclock:inst11\|hour_set0\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.616 ns" { alarmclock:inst11|hour_set0[0]~532 alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.917 ns ( 43.63 % ) " "Info: Total cell delay = 0.917 ns ( 43.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.185 ns ( 56.37 % ) " "Info: Total interconnect delay = 1.185 ns ( 56.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.102 ns" { alarmclock:inst11|hour_set1[1] alarmclock:inst11|hour_set0[0]~530 alarmclock:inst11|hour_set0[0]~532 alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.102 ns" { alarmclock:inst11|hour_set1[1] alarmclock:inst11|hour_set0[0]~530 alarmclock:inst11|hour_set0[0]~532 alarmclock:inst11|hour_set0[2] } { 0.000ns 0.453ns 0.354ns 0.378ns } { 0.000ns 0.454ns 0.225ns 0.238ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 2.111 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 2.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns SW2 1 CLK PIN_10 52 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 52; CLK Node = 'SW2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW2 } "NODE_NAME" } } { "main.bdf" "" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.547 ns) 2.111 ns alarmclock:inst11\|hour_set0\[2\] 2 REG LC_X20_Y5_N5 6 " "Info: 2: + IC(0.434 ns) + CELL(0.547 ns) = 2.111 ns; Loc. = LC_X20_Y5_N5; Fanout = 6; REG Node = 'alarmclock:inst11\|hour_set0\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.981 ns" { SW2 alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.44 % ) " "Info: Total cell delay = 1.677 ns ( 79.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.434 ns ( 20.56 % ) " "Info: Total interconnect delay = 0.434 ns ( 20.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { SW2 alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.111 ns" { SW2 SW2~out0 alarmclock:inst11|hour_set0[2] } { 0.000ns 0.000ns 0.434ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 2.111 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 2.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns SW2 1 CLK PIN_10 52 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 52; CLK Node = 'SW2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW2 } "NODE_NAME" } } { "main.bdf" "" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.547 ns) 2.111 ns alarmclock:inst11\|hour_set1\[1\] 2 REG LC_X20_Y5_N6 5 " "Info: 2: + IC(0.434 ns) + CELL(0.547 ns) = 2.111 ns; Loc. = LC_X20_Y5_N6; Fanout = 5; REG Node = 'alarmclock:inst11\|hour_set1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.981 ns" { SW2 alarmclock:inst11|hour_set1[1] } "NODE_NAME" } } { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.44 % ) " "Info: Total cell delay = 1.677 ns ( 79.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.434 ns ( 20.56 % ) " "Info: Total interconnect delay = 0.434 ns ( 20.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { SW2 alarmclock:inst11|hour_set1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.111 ns" { SW2 SW2~out0 alarmclock:inst11|hour_set1[1] } { 0.000ns 0.000ns 0.434ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { SW2 alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.111 ns" { SW2 SW2~out0 alarmclock:inst11|hour_set0[2] } { 0.000ns 0.000ns 0.434ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { SW2 alarmclock:inst11|hour_set1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.111 ns" { SW2 SW2~out0 alarmclock:inst11|hour_set1[1] } { 0.000ns 0.000ns 0.434ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.102 ns" { alarmclock:inst11|hour_set1[1] alarmclock:inst11|hour_set0[0]~530 alarmclock:inst11|hour_set0[0]~532 alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.102 ns" { alarmclock:inst11|hour_set1[1] alarmclock:inst11|hour_set0[0]~530 alarmclock:inst11|hour_set0[0]~532 alarmclock:inst11|hour_set0[2] } { 0.000ns 0.453ns 0.354ns 0.378ns } { 0.000ns 0.454ns 0.225ns 0.238ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { SW2 alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.111 ns" { SW2 SW2~out0 alarmclock:inst11|hour_set0[2] } { 0.000ns 0.000ns 0.434ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.111 ns" { SW2 alarmclock:inst11|hour_set1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.111 ns" { SW2 SW2~out0 alarmclock:inst11|hour_set1[1] } { 0.000ns 0.000ns 0.434ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { alarmclock:inst11|hour_set0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { alarmclock:inst11|hour_set0[2] } {  } {  } } } { "alarmclock.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/alarmclock.v" 105 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register date_main:inst4\|autodate:inst\|EO1 register date_main:inst4\|datecontrol:inst1\|disp_select\[5\] 69.93 MHz 14.301 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 69.93 MHz between source register \"date_main:inst4\|autodate:inst\|EO1\" and destination register \"date_main:inst4\|datecontrol:inst1\|disp_select\[5\]\" (period= 14.301 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.218 ns + Longest register register " "Info: + Longest register to register delay is 2.218 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_main:inst4\|autodate:inst\|EO1 1 REG LC_X10_Y4_N3 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N3; Fanout = 18; REG Node = 'date_main:inst4\|autodate:inst\|EO1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { date_main:inst4|autodate:inst|EO1 } "NODE_NAME" } } { "autodate.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/autodate.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.615 ns) + CELL(0.225 ns) 1.840 ns date_main:inst4\|datecontrol:inst1\|always0~0 2 COMB LC_X19_Y6_N0 1 " "Info: 2: + IC(1.615 ns) + CELL(0.225 ns) = 1.840 ns; Loc. = LC_X19_Y6_N0; Fanout = 1; COMB Node = 'date_main:inst4\|datecontrol:inst1\|always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.840 ns" { date_main:inst4|autodate:inst|EO1 date_main:inst4|datecontrol:inst1|always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.238 ns) 2.218 ns date_main:inst4\|datecontrol:inst1\|disp_select\[5\] 3 REG LC_X19_Y6_N1 13 " "Info: 3: + IC(0.140 ns) + CELL(0.238 ns) = 2.218 ns; Loc. = LC_X19_Y6_N1; Fanout = 13; REG Node = 'date_main:inst4\|datecontrol:inst1\|disp_select\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.378 ns" { date_main:inst4|datecontrol:inst1|always0~0 date_main:inst4|datecontrol:inst1|disp_select[5] } "NODE_NAME" } } { "datecontrol.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/datecontrol.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.463 ns ( 20.87 % ) " "Info: Total cell delay = 0.463 ns ( 20.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.755 ns ( 79.13 % ) " "Info: Total interconnect delay = 1.755 ns ( 79.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { date_main:inst4|autodate:inst|EO1 date_main:inst4|datecontrol:inst1|always0~0 date_main:inst4|datecontrol:inst1|disp_select[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.218 ns" { date_main:inst4|autodate:inst|EO1 date_main:inst4|datecontrol:inst1|always0~0 date_main:inst4|datecontrol:inst1|disp_select[5] } { 0.000ns 1.615ns 0.140ns } { 0.000ns 0.225ns 0.238ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-11.881 ns - Smallest " "Info: - Smallest clock skew is -11.881 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 5.725 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 5.725 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Clock 1 CLK PIN_66 37 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 37; CLK Node = 'Clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "main.bdf" "" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.720 ns) 2.315 ns fdiv:inst5\|f200hz 2 REG LC_X26_Y6_N6 90 " "Info: 2: + IC(0.465 ns) + CELL(0.720 ns) = 2.315 ns; Loc. = LC_X26_Y6_N6; Fanout = 90; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.185 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } } { "fdiv.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/fdiv.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.863 ns) + CELL(0.547 ns) 5.725 ns date_main:inst4\|datecontrol:inst1\|disp_select\[5\] 3 REG LC_X19_Y6_N1 13 " "Info: 3: + IC(2.863 ns) + CELL(0.547 ns) = 5.725 ns; Loc. = LC_X19_Y6_N1; Fanout = 13; REG Node = 'date_main:inst4\|datecontrol:inst1\|disp_select\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.410 ns" { fdiv:inst5|f200hz date_main:inst4|datecontrol:inst1|disp_select[5] } "NODE_NAME" } } { "datecontrol.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/datecontrol.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 41.87 % ) " "Info: Total cell delay = 2.397 ns ( 41.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.328 ns ( 58.13 % ) " "Info: Total interconnect delay = 3.328 ns ( 58.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.725 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:inst1|disp_select[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.725 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:inst1|disp_select[5] } { 0.000ns 0.000ns 0.465ns 2.863ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 17.606 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 17.606 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Clock 1 CLK PIN_66 37 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 37; CLK Node = 'Clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clock } "NODE_NAME" } } { "main.bdf" "" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.720 ns) 2.315 ns fdiv:inst5\|f200hz 2 REG LC_X26_Y6_N6 90 " "Info: 2: + IC(0.465 ns) + CELL(0.720 ns) = 2.315 ns; Loc. = LC_X26_Y6_N6; Fanout = 90; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.185 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } } { "fdiv.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/fdiv.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.849 ns) + CELL(0.720 ns) 5.884 ns fdiv:inst5\|f1hz 3 REG LC_X10_Y10_N8 1 " "Info: 3: + IC(2.849 ns) + CELL(0.720 ns) = 5.884 ns; Loc. = LC_X10_Y10_N8; Fanout = 1; REG Node = 'fdiv:inst5\|f1hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.569 ns" { fdiv:inst5|f200hz fdiv:inst5|f1hz } "NODE_NAME" } } { "fdiv.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/fdiv.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.088 ns) 6.939 ns stopwatch:inst2\|F_out~8 4 COMB LC_X11_Y6_N6 8 " "Info: 4: + IC(0.967 ns) + CELL(0.088 ns) = 6.939 ns; Loc. = LC_X11_Y6_N6; Fanout = 8; COMB Node = 'stopwatch:inst2\|F_out~8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.055 ns" { fdiv:inst5|f1hz stopwatch:inst2|F_out~8 } "NODE_NAME" } } { "stopwatch.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/stopwatch.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.955 ns) + CELL(0.720 ns) 10.614 ns time_auto_and_set:inst1\|timepiece_main:inst1\|second_counter:inst2\|EO 5 REG LC_X20_Y9_N9 8 " "Info: 5: + IC(2.955 ns) + CELL(0.720 ns) = 10.614 ns; Loc. = LC_X20_Y9_N9; Fanout = 8; REG Node = 'time_auto_and_set:inst1\|timepiece_main:inst1\|second_counter:inst2\|EO'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.675 ns" { stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO } "NODE_NAME" } } { "second_counter.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/second_counter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.720 ns) 12.351 ns time_auto_and_set:inst1\|timepiece_main:inst1\|minute_counter:inst1\|EO 6 REG LC_X21_Y6_N8 7 " "Info: 6: + IC(1.017 ns) + CELL(0.720 ns) = 12.351 ns; Loc. = LC_X21_Y6_N8; Fanout = 7; REG Node = 'time_auto_and_set:inst1\|timepiece_main:inst1\|minute_counter:inst1\|EO'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.737 ns" { time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO } "NODE_NAME" } } { "minute_counter.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/minute_counter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.939 ns) + CELL(0.720 ns) 14.010 ns time_auto_and_set:inst1\|timepiece_main:inst1\|hour_counter:inst\|EO 7 REG LC_X23_Y6_N1 14 " "Info: 7: + IC(0.939 ns) + CELL(0.720 ns) = 14.010 ns; Loc. = LC_X23_Y6_N1; Fanout = 14; REG Node = 'time_auto_and_set:inst1\|timepiece_main:inst1\|hour_counter:inst\|EO'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.659 ns" { time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO } "NODE_NAME" } } { "hour_counter.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/hour_counter.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.049 ns) + CELL(0.547 ns) 17.606 ns date_main:inst4\|autodate:inst\|EO1 8 REG LC_X10_Y4_N3 18 " "Info: 8: + IC(3.049 ns) + CELL(0.547 ns) = 17.606 ns; Loc. = LC_X10_Y4_N3; Fanout = 18; REG Node = 'date_main:inst4\|autodate:inst\|EO1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.596 ns" { time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO date_main:inst4|autodate:inst|EO1 } "NODE_NAME" } } { "autodate.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/autodate.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.365 ns ( 30.47 % ) " "Info: Total cell delay = 5.365 ns ( 30.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.241 ns ( 69.53 % ) " "Info: Total interconnect delay = 12.241 ns ( 69.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.606 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f1hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO date_main:inst4|autodate:inst|EO1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "17.606 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f1hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO date_main:inst4|autodate:inst|EO1 } { 0.000ns 0.000ns 0.465ns 2.849ns 0.967ns 2.955ns 1.017ns 0.939ns 3.049ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.088ns 0.720ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.725 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:inst1|disp_select[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.725 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:inst1|disp_select[5] } { 0.000ns 0.000ns 0.465ns 2.863ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.606 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f1hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO date_main:inst4|autodate:inst|EO1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "17.606 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f1hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO date_main:inst4|autodate:inst|EO1 } { 0.000ns 0.000ns 0.465ns 2.849ns 0.967ns 2.955ns 1.017ns 0.939ns 3.049ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.088ns 0.720ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "autodate.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/autodate.v" 4 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "datecontrol.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/datecontrol.v" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { date_main:inst4|autodate:inst|EO1 date_main:inst4|datecontrol:inst1|always0~0 date_main:inst4|datecontrol:inst1|disp_select[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.218 ns" { date_main:inst4|autodate:inst|EO1 date_main:inst4|datecontrol:inst1|always0~0 date_main:inst4|datecontrol:inst1|disp_select[5] } { 0.000ns 1.615ns 0.140ns } { 0.000ns 0.225ns 0.238ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.725 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:inst1|disp_select[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.725 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:inst1|disp_select[5] } { 0.000ns 0.000ns 0.465ns 2.863ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.606 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f1hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO date_main:inst4|autodate:inst|EO1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "17.606 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f1hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2|EO time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1|EO time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst|EO date_main:inst4|autodate:inst|EO1 } { 0.000ns 0.000ns 0.465ns 2.849ns 0.967ns 2.955ns 1.017ns 0.939ns 3.049ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.088ns 0.720ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}