main.hier_info

是一些很好的FPGA设计实例

|main
alarm <= alarmclock:inst11.alarm
SW3 => maincontrol:inst3.SW3
SW1 => alarmclock:inst11.SW1
SW1 => time_auto_and_set:inst1.SW1
SW1 => date_main:inst4.SW1
SW2 => alarmclock:inst11.SW2
SW2 => time_auto_and_set:inst1.SW2
SW2 => date_main:inst4.SW2
Clock => fdiv:inst5.clk
Clock => time_disp_select:inst6.clk_1khz
disp_data[0] <= disp_data_mux:inst8.disp_data[0]
disp_data[1] <= disp_data_mux:inst8.disp_data[1]
disp_data[2] <= disp_data_mux:inst8.disp_data[2]
disp_data[3] <= disp_data_mux:inst8.disp_data[3]
disp_data[4] <= disp_data_mux:inst8.disp_data[4]
disp_data[5] <= disp_data_mux:inst8.disp_data[5]
disp_data[6] <= disp_data_mux:inst8.disp_data[6]
disp_select[0] <= disp_data_mux:inst8.disp_select[0]
disp_select[1] <= disp_data_mux:inst8.disp_select[1]
disp_select[2] <= disp_data_mux:inst8.disp_select[2]
disp_select[3] <= disp_data_mux:inst8.disp_select[3]
disp_select[4] <= disp_data_mux:inst8.disp_select[4]
disp_select[5] <= disp_data_mux:inst8.disp_select[5]


|main|alarmclock:inst11
clk_200hz => alarmclock_disp_select[4]~reg0.CLK
clk_200hz => alarmclock_disp_select[3]~reg0.CLK
clk_200hz => alarmclock_disp_select[2]~reg0.CLK
clk_200hz => alarmclock_disp_select[1]~reg0.CLK
clk_200hz => alarmclock_disp_select[0]~reg0.CLK
clk_200hz => alarmclock_disp_select[5]~reg0.CLK
EN => disp_drive[1].ENA
EN => disp_drive[0].ENA
EN => disp_drive[2].ENA
SW1 => disp_drive[1].CLK
SW1 => disp_drive[0].CLK
SW1 => disp_drive[2].CLK
SW2 => hour_set1[2].CLK
SW2 => hour_set1[1].CLK
SW2 => hour_set1[0].CLK
SW2 => hour_set0[3].CLK
SW2 => hour_set0[2].CLK
SW2 => hour_set0[1].CLK
SW2 => hour_set0[0].CLK
SW2 => minute_set1[3].CLK
SW2 => minute_set1[2].CLK
SW2 => minute_set1[1].CLK
SW2 => minute_set1[0].CLK
SW2 => minute_set0[3].CLK
SW2 => minute_set0[2].CLK
SW2 => minute_set0[1].CLK
SW2 => minute_set0[0].CLK
SW2 => second_set1[3].CLK
SW2 => second_set1[2].CLK
SW2 => second_set1[1].CLK
SW2 => second_set1[0].CLK
SW2 => second_set0[3].CLK
SW2 => second_set0[2].CLK
SW2 => second_set0[1].CLK
SW2 => second_set0[0].CLK
SW2 => hour_set1[3].CLK
hour1[0] => Equal0.IN3
hour1[1] => Equal0.IN2
hour1[2] => Equal0.IN1
hour1[3] => Equal0.IN0
hour0[0] => Equal1.IN3
hour0[1] => Equal1.IN2
hour0[2] => Equal1.IN1
hour0[3] => Equal1.IN0
minute1[0] => Equal2.IN3
minute1[1] => Equal2.IN2
minute1[2] => Equal2.IN1
minute1[3] => Equal2.IN0
minute0[0] => Equal3.IN3
minute0[1] => Equal3.IN2
minute0[2] => Equal3.IN1
minute0[3] => Equal3.IN0
second1[0] => Equal4.IN3
second1[1] => Equal4.IN2
second1[2] => Equal4.IN1
second1[3] => Equal4.IN0
second0[0] => Equal5.IN3
second0[1] => Equal5.IN2
second0[2] => Equal5.IN1
second0[3] => Equal5.IN0
alarm <= always0~4.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[0] <= alarmclock_disp_select[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[1] <= alarmclock_disp_select[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[2] <= alarmclock_disp_select[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[3] <= alarmclock_disp_select[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[4] <= alarmclock_disp_select[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarmclock_disp_select[5] <= alarmclock_disp_select[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|main|maincontrol:inst3
SW3 => Function[1].CLK
SW3 => Function[0].CLK
SW3 => Timepiece_EN~reg0.CLK
SW3 => TimeSet_EN~reg0.CLK
SW3 => Stopwatch_EN~reg0.CLK
SW3 => Alarmclock_EN~reg0.CLK
SW3 => Date_EN~reg0.CLK
SW3 => DateSet_EN~reg0.CLK
SW3 => Function[2].CLK
Timepiece_EN <= Timepiece_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimeSet_EN <= TimeSet_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE
Stopwatch_EN <= Stopwatch_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE
Alarmclock_EN <= Alarmclock_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE
Date_EN <= Date_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE
DateSet_EN <= DateSet_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE


|main|fdiv:inst5
clk => CNT1[30].CLK
clk => CNT1[29].CLK
clk => CNT1[28].CLK
clk => CNT1[27].CLK
clk => CNT1[26].CLK
clk => CNT1[25].CLK
clk => CNT1[24].CLK
clk => CNT1[23].CLK
clk => CNT1[22].CLK
clk => CNT1[21].CLK
clk => CNT1[20].CLK
clk => CNT1[19].CLK
clk => CNT1[18].CLK
clk => CNT1[17].CLK
clk => CNT1[16].CLK
clk => CNT1[15].CLK
clk => CNT1[14].CLK
clk => CNT1[13].CLK
clk => CNT1[12].CLK
clk => CNT1[11].CLK
clk => CNT1[10].CLK
clk => CNT1[9].CLK
clk => CNT1[8].CLK
clk => CNT1[7].CLK
clk => CNT1[6].CLK
clk => CNT1[5].CLK
clk => CNT1[4].CLK
clk => CNT1[3].CLK
clk => CNT1[2].CLK
clk => CNT1[1].CLK
clk => CNT1[0].CLK
clk => f200hz~reg0.CLK
clk => CNT1[31].CLK
f200hz <= f200hz~reg0.DB_MAX_OUTPUT_PORT_TYPE
f60hz <= f60hz~reg0.DB_MAX_OUTPUT_PORT_TYPE
f1hz <= f1hz~reg0.DB_MAX_OUTPUT_PORT_TYPE


|main|time_auto_and_set:inst1
day_EN <= timepiece_main:inst1.day_EN
Timepiece_EN => timepiece_main:inst1.Timepiece_EN
CLK => timepiece_main:inst1.CLK
hour_0[0] <= time_mux:inst.hour_0[0]
hour_0[1] <= time_mux:inst.hour_0[1]
hour_0[2] <= time_mux:inst.hour_0[2]
hour_0[3] <= time_mux:inst.hour_0[3]
SW1 => time_mux:inst.TimeSet_EN
SW1 => timeset:inst2.SW1
Timeset_EN => timeset:inst2.TimeSet_EN
SW2 => timeset:inst2.SW2
hour_1[0] <= time_mux:inst.hour_1[0]
hour_1[1] <= time_mux:inst.hour_1[1]
hour_1[2] <= time_mux:inst.hour_1[2]
hour_1[3] <= time_mux:inst.hour_1[3]
minute_0[0] <= time_mux:inst.minute_0[0]
minute_0[1] <= time_mux:inst.minute_0[1]
minute_0[2] <= time_mux:inst.minute_0[2]
minute_0[3] <= time_mux:inst.minute_0[3]
minute_1[0] <= time_mux:inst.minute_1[0]
minute_1[1] <= time_mux:inst.minute_1[1]
minute_1[2] <= time_mux:inst.minute_1[2]
minute_1[3] <= time_mux:inst.minute_1[3]
second_0[0] <= time_mux:inst.second_0[0]
second_0[1] <= time_mux:inst.second_0[1]
second_0[2] <= time_mux:inst.second_0[2]
second_0[3] <= time_mux:inst.second_0[3]
second_1[0] <= time_mux:inst.second_1[0]
second_1[1] <= time_mux:inst.second_1[1]
second_1[2] <= time_mux:inst.second_1[2]
second_1[3] <= time_mux:inst.second_1[3]
TimeSet_disp_drive[0] <= timeset:inst2.disp_drive[0]
TimeSet_disp_drive[1] <= timeset:inst2.disp_drive[1]
TimeSet_disp_drive[2] <= timeset:inst2.disp_drive[2]


|main|time_auto_and_set:inst1|timepiece_main:inst1
day_EN <= hour_counter:inst.EO
Timepiece_EN => minute_counter:inst1.EN
Timepiece_EN => second_counter:inst2.EN
Timepiece_EN => hour_counter:inst.EN
CLK => second_counter:inst2.clk
hour0[0] <= hour_counter:inst.hour_data0[0]
hour0[1] <= hour_counter:inst.hour_data0[1]
hour0[2] <= hour_counter:inst.hour_data0[2]
hour0[3] <= hour_counter:inst.hour_data0[3]
hour1[0] <= hour_counter:inst.hour_data1[0]
hour1[1] <= hour_counter:inst.hour_data1[1]
hour1[2] <= hour_counter:inst.hour_data1[2]
hour1[3] <= hour_counter:inst.hour_data1[3]
minute0[0] <= minute_counter:inst1.minute_data0[0]
minute0[1] <= minute_counter:inst1.minute_data0[1]
minute0[2] <= minute_counter:inst1.minute_data0[2]
minute0[3] <= minute_counter:inst1.minute_data0[3]
minute1[0] <= minute_counter:inst1.minute_data1[0]
minute1[1] <= minute_counter:inst1.minute_data1[1]
minute1[2] <= minute_counter:inst1.minute_data1[2]
minute1[3] <= minute_counter:inst1.minute_data1[3]
second0[0] <= second_counter:inst2.second_data0[0]
second0[1] <= second_counter:inst2.second_data0[1]
second0[2] <= second_counter:inst2.second_data0[2]
second0[3] <= second_counter:inst2.second_data0[3]
second1[0] <= second_counter:inst2.second_data1[0]
second1[1] <= second_counter:inst2.second_data1[1]
second1[2] <= second_counter:inst2.second_data1[2]
second1[3] <= second_counter:inst2.second_data1[3]


|main|time_auto_and_set:inst1|timepiece_main:inst1|hour_counter:inst
clk => hour_data0[2]~reg0.CLK
clk => hour_data0[1]~reg0.CLK
clk => hour_data0[0]~reg0.CLK
clk => EO~reg0.CLK
clk => hour_data1[3]~reg0.CLK
clk => hour_data1[2]~reg0.CLK
clk => hour_data1[1]~reg0.CLK
clk => hour_data1[0]~reg0.CLK
clk => hour_data0[3]~reg0.CLK
EN => hour_data0[2]~reg0.ENA
EN => hour_data0[1]~reg0.ENA
EN => hour_data0[0]~reg0.ENA
EN => hour_data0[3]~reg0.ENA
hour_data1[0] <= hour_data1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data1[1] <= hour_data1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data1[2] <= hour_data1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data1[3] <= hour_data1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[0] <= hour_data0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[1] <= hour_data0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[2] <= hour_data0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[3] <= hour_data0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
EO <= EO~reg0.DB_MAX_OUTPUT_PORT_TYPE


|main|time_auto_and_set:inst1|timepiece_main:inst1|minute_counter:inst1
EN => minute_data0[2]~reg0.ENA
EN => minute_data0[1]~reg0.ENA
EN => minute_data0[0]~reg0.ENA
EN => minute_data0[3]~reg0.ENA
clk => minute_data0[2]~reg0.CLK
clk => minute_data0[1]~reg0.CLK
clk => minute_data0[0]~reg0.CLK
clk => EO~reg0.CLK
clk => minute_data1[3]~reg0.CLK
clk => minute_data1[2]~reg0.CLK
clk => minute_data1[1]~reg0.CLK
clk => minute_data1[0]~reg0.CLK
clk => minute_data0[3]~reg0.CLK
minute_data1[0] <= minute_data1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
minute_data1[1] <= minute_data1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
minute_data1[2] <= minute_data1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
minute_data1[3] <= minute_data1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
minute_data0[0] <= minute_data0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
minute_data0[1] <= minute_data0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
minute_data0[2] <= minute_data0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
minute_data0[3] <= minute_data0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
EO <= EO~reg0.DB_MAX_OUTPUT_PORT_TYPE


|main|time_auto_and_set:inst1|timepiece_main:inst1|second_counter:inst2
EN => second_data0[2]~reg0.ENA
EN => second_data0[1]~reg0.ENA
EN => second_data0[0]~reg0.ENA
EN => second_data0[3]~reg0.ENA
clk => second_data0[2]~reg0.CLK
clk => second_data0[1]~reg0.CLK
clk => second_data0[0]~reg0.CLK
clk => EO~reg0.CLK
clk => second_data1[3]~reg0.CLK
clk => second_data1[2]~reg0.CLK
clk => second_data1[1]~reg0.CLK
clk => second_data1[0]~reg0.CLK
clk => second_data0[3]~reg0.CLK
second_data1[0] <= second_data1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data1[1] <= second_data1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data1[2] <= second_data1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data1[3] <= second_data1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data0[0] <= second_data0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data0[1] <= second_data0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second_data0[2] <= second_data0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE