main.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "time_auto_and_set time_auto_and_set:inst1 " "Info: Elaborating entity \"time_auto_and_set\" for hierarchy \"time_auto_and_set:inst1\"" {  } { { "main.bdf" "inst1" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { -8 520 768 184 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timepiece_main time_auto_and_set:inst1\|timepiece_main:inst1 " "Info: Elaborating entity \"timepiece_main\" for hierarchy \"time_auto_and_set:inst1\|timepiece_main:inst1\"" {  } { { "time_auto_and_set.bdf" "inst1" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/time_auto_and_set.bdf" { { 40 -16 208 200 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour_counter time_auto_and_set:inst1\|timepiece_main:inst1\|hour_counter:inst " "Info: Elaborating entity \"hour_counter\" for hierarchy \"time_auto_and_set:inst1\|timepiece_main:inst1\|hour_counter:inst\"" {  } { { "timepiece_main.bdf" "inst" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/timepiece_main.bdf" { { 48 560 712 144 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute_counter time_auto_and_set:inst1\|timepiece_main:inst1\|minute_counter:inst1 " "Info: Elaborating entity \"minute_counter\" for hierarchy \"time_auto_and_set:inst1\|timepiece_main:inst1\|minute_counter:inst1\"" {  } { { "timepiece_main.bdf" "inst1" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/timepiece_main.bdf" { { 168 360 520 264 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second_counter time_auto_and_set:inst1\|timepiece_main:inst1\|second_counter:inst2 " "Info: Elaborating entity \"second_counter\" for hierarchy \"time_auto_and_set:inst1\|timepiece_main:inst1\|second_counter:inst2\"" {  } { { "timepiece_main.bdf" "inst2" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/timepiece_main.bdf" { { 280 144 304 376 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "time_mux time_auto_and_set:inst1\|time_mux:inst " "Info: Elaborating entity \"time_mux\" for hierarchy \"time_auto_and_set:inst1\|time_mux:inst\"" {  } { { "time_auto_and_set.bdf" "inst" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/time_auto_and_set.bdf" { { -152 608 824 104 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timeset time_auto_and_set:inst1\|timeset:inst2 " "Info: Elaborating entity \"timeset\" for hierarchy \"time_auto_and_set:inst1\|timeset:inst2\"" {  } { { "time_auto_and_set.bdf" "inst2" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/time_auto_and_set.bdf" { { 0 328 536 192 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "timeset.v(32) " "Warning (10101): Verilog HDL unsupported feature warning at timeset.v(32): Initial Construct is not supported and will be ignored" {  } { { "timeset.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/timeset.v" 32 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "stopwatch stopwatch:inst2 " "Info: Elaborating entity \"stopwatch\" for hierarchy \"stopwatch:inst2\"" {  } { { "main.bdf" "inst2" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { -8 344 440 88 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "disp_data_mux disp_data_mux:inst8 " "Info: Elaborating entity \"disp_data_mux\" for hierarchy \"disp_data_mux:inst8\"" {  } { { "main.bdf" "inst8" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { 456 944 1216 808 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "disp_data_mux.v(60) " "Info (10264): Verilog HDL Case Statement information at disp_data_mux.v(60): all case item expressions in this case statement are onehot" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 60 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "disp_data_mux.v(74) " "Info (10264): Verilog HDL Case Statement information at disp_data_mux.v(74): all case item expressions in this case statement are onehot" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 74 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "disp_data_mux.v(88) " "Info (10264): Verilog HDL Case Statement information at disp_data_mux.v(88): all case item expressions in this case statement are onehot" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 88 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data disp_data_mux.v(97) " "Warning (10235): Verilog HDL Always Construct warning at disp_data_mux.v(97): variable \"Data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 97 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "disp_select disp_data_mux.v(40) " "Warning (10240): Verilog HDL Always Construct warning at disp_data_mux.v(40): inferring latch(es) for variable \"disp_select\", which holds its previous value in one or more paths through the always construct" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 40 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "disp_select\[5\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"disp_select\[5\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "disp_select\[4\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"disp_select\[4\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "disp_select\[3\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"disp_select\[3\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "disp_select\[2\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"disp_select\[2\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "disp_select\[1\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"disp_select\[1\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "disp_select\[0\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"disp_select\[0\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "Data disp_data_mux.v(40) " "Warning (10240): Verilog HDL Always Construct warning at disp_data_mux.v(40): inferring latch(es) for variable \"Data\", which holds its previous value in one or more paths through the always construct" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 40 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Data\[3\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"Data\[3\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Data\[2\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"Data\[2\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Data\[1\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"Data\[1\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "Data\[0\] disp_data_mux.v(57) " "Info (10041): Verilog HDL or VHDL info at disp_data_mux.v(57): inferred latch for \"Data\[0\]\"" {  } { { "disp_data_mux.v" "" { Text "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/disp_data_mux.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "date_main.bdf 1 1 " "Warning: Using design file date_main.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 date_main " "Info: Found entity 1: date_main" {  } { { "date_main.bdf" "" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/date_main.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "date_main date_main:inst4 " "Info: Elaborating entity \"date_main\" for hierarchy \"date_main:inst4\"" {  } { { "main.bdf" "inst4" { Schematic "C:/Documents and Settings/zhang/桌面/多功能数字钟/main/main.bdf" { { 288 528 784 448 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}