main.fit.summary

是一些很好的FPGA设计实例

Fitter Status : Successful - Mon May 26 19:43:06 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : main
Top-level Entity Name : main
Family : ACEX1K
Device : EP1K10TC100-1
Timing Models : Final
Total logic elements : 211 / 576 ( 37 % )
Total pins : 60 / 66 ( 91 % )
Total memory bits : 0 / 12,288 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )