main.v

是一些很好的FPGA设计实例

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

module main(
	Reset,
	Clock_8MHz,
	Acceleration,
	Initial_Speed,
	Step_Sum,
	Pulse_Wave
);

input	Reset;
input	Clock_8MHz;
input	[16:0] Acceleration;
input	[15:0] Initial_Speed;
input	[23:0] Step_Sum;
output	Pulse_Wave;

wire	SYNTHESIZED_WIRE_7;
wire	[15:0] SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	[15:0] SYNTHESIZED_WIRE_4;
wire	[15:0] SYNTHESIZED_WIRE_5;
wire	SYNTHESIZED_WIRE_6;





fdiv	b2v_inst(.Reset(Reset),
.Clock_8MHz(Clock_8MHz),.F_65536Hz(SYNTHESIZED_WIRE_7),.F_1Hz(SYNTHESIZED_WIRE_2));

counter_16_bits	b2v_inst1(.Clk_65536Hz(SYNTHESIZED_WIRE_7),
.Reset(Reset),.counter_out(SYNTHESIZED_WIRE_1));

pulse_16	b2v_inst2(.Reset(Reset),
.counter_data(SYNTHESIZED_WIRE_1),.pulse_16_out(SYNTHESIZED_WIRE_4));

second_pulse_latch	b2v_inst3(.Reset(Reset),
.Clk_1Hz(SYNTHESIZED_WIRE_2),.acceleration(Acceleration),.speed(Initial_Speed),.second_pulse_out(SYNTHESIZED_WIRE_5));

pulse_sum	b2v_inst4(.Reset(Reset),
.Clock_65536Hz(SYNTHESIZED_WIRE_7),.pulse_16_data(SYNTHESIZED_WIRE_4),.second_pulse_data(SYNTHESIZED_WIRE_5),.pulse_out(SYNTHESIZED_WIRE_6));

sum_control	b2v_inst5(.Reset(Reset),
.pulse_sum_in(SYNTHESIZED_WIRE_6),.step_sum(Step_Sum),.wave_out(Pulse_Wave));


endmodule