📄 main.fit.rpt
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+----------------+
; Cascade Chains ;
+--------+-------+
; Length ; Count ;
+--------+-------+
; 2 ; 11 ;
+--------+-------+
+--------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------------------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+----------------------------------------------------------------------------------------------------------+---------+
; Reset ; 36 ;
; sum_control:inst5|step_counter[22]~967 ; 24 ;
; Reset~$wirecell ; 24 ;
; fdiv:inst|CNT~271 ; 23 ;
; fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; 20 ;
; fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT ; 17 ;
; counter_16_bits:inst1|LessThan0~178 ; 16 ;
; Acceleration[16] ; 15 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT ; 5 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT ; 5 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ; 5 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT ; 5 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT ; 5 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT ; 5 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT ; 4 ;
; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT ; 4 ;
; second_pulse_latch:inst3|second_pulse_out[9]~917 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[6]~909 ; 3 ;
; pulse_sum:inst4|pulse_1~434 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[3]~912 ; 3 ;
; pulse_sum:inst4|pulse_1~431 ; 3 ;
; pulse_sum:inst4|pulse_1~428 ; 3 ;
; pulse_sum:inst4|pulse_1~429 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[10]~916 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[5]~910 ; 3 ;
; pulse_sum:inst4|pulse_1~427 ; 3 ;
; pulse_sum:inst4|pulse_1~426 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[0]~915 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[8]~918 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[11]~923 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[4]~911 ; 3 ;
; second_pulse_latch:inst3|second_pulse_out[2]~913 ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[22]~COUT ; 3 ;
; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT ; 3 ;
+----------------------------------------------------------------------------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------+
; Peripheral Signals ;
+-------------------------------+---------+-------+-----------------+---------------------------+----------+
; Peripheral Signal ; Source ; Usage ; Dedicated Clock ; Peripheral Control Signal ; Polarity ;
+-------------------------------+---------+-------+-----------------+---------------------------+----------+
; pulse_sum:inst4|pulse_out~128 ; LC1_C11 ; Clock ; no ; yes ; +ve ;
+-------------------------------+---------+-------+-----------------+---------------------------+----------+
+-------------------------------------------+
; LAB ;
+--------------------------+----------------+
; Number of Logic Elements ; Number of LABs ;
+--------------------------+----------------+
; 0 ; 42 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 4 ;
; 7 ; 2 ;
; 8 ; 20 ;
+--------------------------+----------------+
+----------------------------------------------+
; Local Routing Interconnect ;
+-----------------------------+----------------+
; Local Routing Interconnects ; Number of LABs ;
+-----------------------------+----------------+
; 0 ; 59 ;
; 1 ; 2 ;
; 2 ; 4 ;
; 3 ; 1 ;
; 4 ; 4 ;
; 5 ; 1 ;
; 6 ; 1 ;
+-----------------------------+----------------+
+---------------------------------------------+
; LAB External Interconnect ;
+----------------------------+----------------+
; LAB External Interconnects ; Number of LABs ;
+----------------------------+----------------+
; 0 - 1 ; 46 ;
; 2 - 3 ; 5 ;
; 4 - 5 ; 1 ;
; 6 - 7 ; 1 ;
; 8 - 9 ; 8 ;
; 10 - 11 ; 0 ;
; 12 - 13 ; 2 ;
; 14 - 15 ; 0 ;
; 16 - 17 ; 6 ;
; 18 - 19 ; 1 ;
; 20 - 21 ; 2 ;
+----------------------------+----------------+
+------------------------------------------------------------------------------------------+
; Row Interconnect ;
+-------+---------------------+-----------------------------+------------------------------+
; Row ; Interconnect Used ; Left Half Interconnect Used ; Right Half Interconnect Used ;
+-------+---------------------+-----------------------------+------------------------------+
; A ; 54 / 96 ( 56 % ) ; 6 / 48 ( 13 % ) ; 0 / 48 ( 0 % ) ;
; B ; 65 / 96 ( 68 % ) ; 5 / 48 ( 10 % ) ; 34 / 48 ( 71 % ) ;
; C ; 28 / 96 ( 29 % ) ; 30 / 48 ( 63 % ) ; 0 / 48 ( 0 % ) ;
; Total ; 147 / 288 ( 51 % ) ; 41 / 144 ( 28 % ) ; 34 / 144 ( 24 % ) ;
+-------+---------------------+-----------------------------+------------------------------+
+---------------------------+
; LAB Column Interconnect ;
+-------+-------------------+
; Col. ; Interconnect Used ;
+-------+-------------------+
; 1 ; 9 / 24 ( 38 % ) ;
; 2 ; 3 / 24 ( 13 % ) ;
; 3 ; 2 / 24 ( 8 % ) ;
; 4 ; 0 / 24 ( 0 % ) ;
; 5 ; 4 / 24 ( 17 % ) ;
; 6 ; 1 / 24 ( 4 % ) ;
; 7 ; 1 / 24 ( 4 % ) ;
; 8 ; 0 / 24 ( 0 % ) ;
; 9 ; 1 / 24 ( 4 % ) ;
; 10 ; 0 / 24 ( 0 % ) ;
; 11 ; 1 / 24 ( 4 % ) ;
; 12 ; 0 / 24 ( 0 % ) ;
; 13 ; 1 / 24 ( 4 % ) ;
; 14 ; 1 / 24 ( 4 % ) ;
; 15 ; 1 / 24 ( 4 % ) ;
; 16 ; 1 / 24 ( 4 % ) ;
; 17 ; 2 / 24 ( 8 % ) ;
; 18 ; 1 / 24 ( 4 % ) ;
; 19 ; 2 / 24 ( 8 % ) ;
; 20 ; 1 / 24 ( 4 % ) ;
; 21 ; 2 / 24 ( 8 % ) ;
; 22 ; 1 / 24 ( 4 % ) ;
; 23 ; 2 / 24 ( 8 % ) ;
; 24 ; 2 / 24 ( 8 % ) ;
; Total ; 39 / 576 ( 7 % ) ;
+-------+-------------------+
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