main.fit.eqn

是一些很好的FPGA设计实例

E1_second_pulse_out[8] = DFFEA(E1_second_pulse_out[8]_lut_out, J1_q[3], , , , , );


--F1L52 is pulse_sum:inst4|pulse_1~17 at LC2_A11
--operation mode is normal

F1L52 = !J2_q[6] & J2_q[7] & E1_second_pulse_out[8] & F1L33;


--F1_pulse_1[8] is pulse_sum:inst4|pulse_1[8] at LC2_A12
--operation mode is normal

F1_pulse_1[8] = Reset & F1_pulse_1[8] # !Reset & F1L52;


--E1_second_pulse_out[7] is second_pulse_latch:inst3|second_pulse_out[7] at LC4_A23
--operation mode is normal

E1_second_pulse_out[7]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[8] # !Acceleration[16] & N6_cs_buffer[7];
E1_second_pulse_out[7] = DFFEA(E1_second_pulse_out[7]_lut_out, J1_q[3], , , , , );


--F1L42 is pulse_sum:inst4|pulse_1~15 at LC4_A9
--operation mode is normal

F1L42 = J2_q[8] & E1_second_pulse_out[7] & F1L43;


--F1_pulse_1[7] is pulse_sum:inst4|pulse_1[7] at LC3_A12
--operation mode is normal

F1_pulse_1[7] = Reset & F1_pulse_1[7] # !Reset & F1L42;


--E1_second_pulse_out[14] is second_pulse_latch:inst3|second_pulse_out[14] at LC3_A23
--operation mode is normal

E1_second_pulse_out[14]_lut_out = !Reset & Acceleration[16] & !L1_unreg_res_node[15] # !Acceleration[16] & L2_unreg_res_node[14];
E1_second_pulse_out[14] = DFFEA(E1_second_pulse_out[14]_lut_out, J1_q[3], , , , , );


--F1L83 is pulse_sum:inst4|pulse_1~425 at LC4_A2
--operation mode is normal

F1L83 = !J2_q[0] & J2_q[1] & E1_second_pulse_out[14] & J1_q[1];


--F1_pulse_1[14] is pulse_sum:inst4|pulse_1[14] at LC6_A12
--operation mode is normal

F1_pulse_1[14] = Reset & F1_pulse_1[14] # !Reset & F1L83;


--E1_second_pulse_out[13] is second_pulse_latch:inst3|second_pulse_out[13] at LC3_A17
--operation mode is normal

E1_second_pulse_out[13]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[14] # !Acceleration[16] & N6_cs_buffer[13];
E1_second_pulse_out[13] = DFFEA(E1_second_pulse_out[13]_lut_out, J1_q[3], , , , , );


--F1L03 is pulse_sum:inst4|pulse_1~27 at LC3_A2
--operation mode is normal

F1L03 = F1L13 & E1_second_pulse_out[13] & J2_q[2];


--F1_pulse_1[13] is pulse_sum:inst4|pulse_1[13] at LC7_A12
--operation mode is normal

F1_pulse_1[13] = Reset & F1_pulse_1[13] # !Reset & F1L03;


--E1_second_pulse_out[12] is second_pulse_latch:inst3|second_pulse_out[12] at LC5_A23
--operation mode is normal

E1_second_pulse_out[12]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[13] # !Acceleration[16] & N6_cs_buffer[12];
E1_second_pulse_out[12] = DFFEA(E1_second_pulse_out[12]_lut_out, J1_q[3], , , , , );


--F1L92 is pulse_sum:inst4|pulse_1~25 at LC7_A2
--operation mode is normal

F1L92 = !J2_q[2] & J2_q[3] & E1_second_pulse_out[12] & F1L13;


--F1_pulse_1[12] is pulse_sum:inst4|pulse_1[12] at LC1_A2
--operation mode is normal

F1_pulse_1[12] = Reset & F1_pulse_1[12] # !Reset & F1L92;


--E1_second_pulse_out[11] is second_pulse_latch:inst3|second_pulse_out[11] at LC4_A17
--operation mode is normal

E1_second_pulse_out[11]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[12] # !Acceleration[16] & N6_cs_buffer[11];
E1_second_pulse_out[11] = DFFEA(E1_second_pulse_out[11]_lut_out, J1_q[3], , , , , );


--F1L82 is pulse_sum:inst4|pulse_1~23 at LC1_A11
--operation mode is normal

F1L82 = J2_q[4] & E1_second_pulse_out[11] & F1L23;


--F1_pulse_1[11] is pulse_sum:inst4|pulse_1[11] at LC8_A12
--operation mode is normal

F1_pulse_1[11] = Reset & F1_pulse_1[11] # !Reset & F1L82;


--A1L04 is rtl~0 at LC1_B6
--operation mode is normal

A1L04 = G1L11 # Reset # !G1L22 # !G1L32;


--J1_q[18] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[18] at LC4_C11
--operation mode is clrb_cntr

J1_q[18]_lut_out = (J1_q[18] $ J1L73) & B1L1;
J1_q[18] = DFFEA(J1_q[18]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L93 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[18]~COUT at LC4_C11
--operation mode is clrb_cntr

J1L93 = CARRY(J1_q[18] & J1L73);


--J1_q[15] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[15] at LC1_C11
--operation mode is clrb_cntr

J1_q[15]_lut_out = (J1_q[15] $ J1L13) & B1L1;
J1_q[15] = DFFEA(J1_q[15]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L33 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT at LC1_C11
--operation mode is clrb_cntr

J1L33 = CARRY(J1_q[15] & J1L13);


--J1_q[14] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[14] at LC8_C9
--operation mode is clrb_cntr

J1_q[14]_lut_out = (J1_q[14] $ J1L92) & B1L1;
J1_q[14] = DFFEA(J1_q[14]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L13 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT at LC8_C9
--operation mode is clrb_cntr

J1L13 = CARRY(J1_q[14] & J1L92);


--J1_q[13] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[13] at LC7_C9
--operation mode is clrb_cntr

J1_q[13]_lut_out = (J1_q[13] $ J1L72) & B1L1;
J1_q[13] = DFFEA(J1_q[13]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L92 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT at LC7_C9
--operation mode is clrb_cntr

J1L92 = CARRY(J1_q[13] & J1L72);


--J1_q[12] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12] at LC6_C9
--operation mode is clrb_cntr

J1_q[12]_lut_out = (J1_q[12] $ J1L52) & B1L1;
J1_q[12] = DFFEA(J1_q[12]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L72 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT at LC6_C9
--operation mode is clrb_cntr

J1L72 = CARRY(J1_q[12] & J1L52);


--B1L3 is fdiv:inst|CNT~259 at LC1_C10
--operation mode is normal

B1L3 = !J1_q[12] & !J1_q[13] & !J1_q[14] & !J1_q[15];


--J1_q[17] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[17] at LC3_C11
--operation mode is clrb_cntr

J1_q[17]_lut_out = (J1_q[17] $ J1L53) & B1L1;
J1_q[17] = DFFEA(J1_q[17]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L73 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT at LC3_C11
--operation mode is clrb_cntr

J1L73 = CARRY(J1_q[17] & J1L53);


--J1_q[16] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[16] at LC2_C11
--operation mode is clrb_cntr

J1_q[16]_lut_out = (J1_q[16] $ J1L33) & B1L1;
J1_q[16] = DFFEA(J1_q[16]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L53 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT at LC2_C11
--operation mode is clrb_cntr

J1L53 = CARRY(J1_q[16] & J1L33);


--B1L5 is fdiv:inst|CNT~263 at LC2_C10
--operation mode is normal

B1L5 = (!J1_q[16] & !J1_q[17] & !J1_q[18] & !J1_q[19]) & CASCADE(B1L3);


--J1_q[7] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[7] at LC1_C9
--operation mode is clrb_cntr

J1_q[7]_lut_out = (J1_q[7] $ J1L51) & B1L1;
J1_q[7] = DFFEA(J1_q[7]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L71 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT at LC1_C9
--operation mode is clrb_cntr

J1L71 = CARRY(J1_q[7] & J1L51);


--J1_q[6] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[6] at LC8_C7
--operation mode is clrb_cntr

J1_q[6]_lut_out = (J1_q[6] $ J1L31) & B1L1;
J1_q[6] = DFFEA(J1_q[6]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L51 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT at LC8_C7
--operation mode is clrb_cntr

J1L51 = CARRY(J1_q[6] & J1L31);


--J1_q[5] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[5] at LC7_C7
--operation mode is clrb_cntr

J1_q[5]_lut_out = (J1_q[5] $ J1L11) & B1L1;
J1_q[5] = DFFEA(J1_q[5]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L31 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT at LC7_C7
--operation mode is clrb_cntr

J1L31 = CARRY(J1_q[5] & J1L11);


--J1_q[4] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[4] at LC6_C7
--operation mode is clrb_cntr

J1_q[4]_lut_out = (J1_q[4] $ J1L9) & B1L1;
J1_q[4] = DFFEA(J1_q[4]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L11 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT at LC6_C7
--operation mode is clrb_cntr

J1L11 = CARRY(J1_q[4] & J1L9);


--B1L4 is fdiv:inst|CNT~261 at LC3_C6
--operation mode is normal

B1L4 = !J1_q[4] & !J1_q[5] & !J1_q[6] & !J1_q[7];


--J1_q[11] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[11] at LC5_C9
--operation mode is clrb_cntr

J1_q[11]_lut_out = (J1_q[11] $ J1L32) & B1L1;
J1_q[11] = DFFEA(J1_q[11]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L52 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT at LC5_C9
--operation mode is clrb_cntr

J1L52 = CARRY(J1_q[11] & J1L32);


--J1_q[10] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[10] at LC4_C9
--operation mode is clrb_cntr

J1_q[10]_lut_out = (J1_q[10] $ J1L12) & B1L1;
J1_q[10] = DFFEA(J1_q[10]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L32 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT at LC4_C9
--operation mode is clrb_cntr

J1L32 = CARRY(J1_q[10] & J1L12);


--J1_q[9] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[9] at LC3_C9
--operation mode is clrb_cntr

J1_q[9]_lut_out = (J1_q[9] $ J1L91) & B1L1;
J1_q[9] = DFFEA(J1_q[9]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L12 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT at LC3_C9
--operation mode is clrb_cntr

J1L12 = CARRY(J1_q[9] & J1L91);


--J1_q[8] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[8] at LC2_C9
--operation mode is clrb_cntr

J1_q[8]_lut_out = (J1_q[8] $ J1L71) & B1L1;
J1_q[8] = DFFEA(J1_q[8]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L91 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT at LC2_C9
--operation mode is clrb_cntr

J1L91 = CARRY(J1_q[8] & J1L71);


--B1L6 is fdiv:inst|CNT~264 at LC4_C6
--operation mode is normal

B1L6 = (!J1_q[8] & !J1_q[9] & !J1_q[10] & !J1_q[11]) & CASCADE(B1L4);


--N6_cs_buffer[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC4_A18
--operation mode is arithmetic

N6_cs_buffer[10] = E1_second_pulse_out[10] $ Acceleration[10] $ N6_cout[9];

--N6_cout[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] at LC4_A18
--operation mode is arithmetic

N6_cout[10] = CARRY(E1_second_pulse_out[10] & Acceleration[10] # N6_cout[9] # !E1_second_pulse_out[10] & Acceleration[10] & N6_cout[9]);


--N3_cs_buffer[11] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC4_A21
--operation mode is arithmetic

N3_cs_buffer[11] = E1_second_pulse_out[10] $ Acceleration[10] $ N3_cout[10];

--N3_cout[11] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] at LC4_A21
--operation mode is arithmetic

N3_cout[11] = CARRY(E1_second_pulse_out[10] & N3_cout[10] # !Acceleration[10] # !E1_second_pulse_out[10] & !Acceleration[10] & N3_cout[10]);


--N6_cs_buffer[9] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC3_A18
--operation mode is arithmetic

N6_cs_buffer[9] = E1_second_pulse_out[9] $ Acceleration[9] $ N6_cout[8];

--N6_cout[9] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] at LC3_A18
--operation mode is arithmetic

N6_cout[9] = CARRY(E1_second_pulse_out[9] & Acceleration[9] # N6_cout[8] # !E1_second_pulse_out[9] & Acceleration[9] & N6_cout[8]);


--N3_cs_buffer[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC3_A21
--operation mode is arithmetic

N3_cs_buffer[10] = E1_second_pulse_out[9] $ Acceleration[9] $ N3_cout[9];

--N3_cout[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] at LC3_A21
--operation mode is arithmetic