main.fit.eqn

是一些很好的FPGA设计实例

--J2L13 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT at LC7_A5
--operation mode is clrb_cntr

J2L13 = CARRY(J2_q[14] & J2L92);


--F1L81 is pulse_sum:inst4|pulse_1~3 at LC4_A10
--operation mode is normal

F1L81 = J2_q[14] & E1_second_pulse_out[1] & F1L73;


--F1_pulse_1[1] is pulse_sum:inst4|pulse_1[1] at LC5_A10
--operation mode is normal

F1_pulse_1[1] = Reset & F1_pulse_1[1] # !Reset & F1L81;


--E1_second_pulse_out[0] is second_pulse_latch:inst3|second_pulse_out[0] at LC1_A16
--operation mode is normal

E1_second_pulse_out[0]_lut_out = !Reset & Acceleration[16] & N3_cs_buffer[1] # !Acceleration[16] & N6_cs_buffer[0];
E1_second_pulse_out[0] = DFFEA(E1_second_pulse_out[0]_lut_out, J1_q[3], , , , , );


--J2_q[15] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[15] at LC8_A5
--operation mode is clrb_cntr

J2_q[15]_lut_out = (J2_q[15] $ J2L13) & C1L5;
J2_q[15] = DFFEA(J2_q[15]_lut_out, J1_q[1], , , , , );


--F1L71 is pulse_sum:inst4|pulse_1~1 at LC7_A10
--operation mode is normal

F1L71 = !J2_q[14] & J2_q[15] & E1_second_pulse_out[0] & F1L73;


--F1_pulse_1[0] is pulse_sum:inst4|pulse_1[0] at LC8_A10
--operation mode is normal

F1_pulse_1[0] = Reset & F1_pulse_1[0] # !Reset & F1L71;


--J1_q[3] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[3] at LC5_C7
--operation mode is clrb_cntr

J1_q[3]_lut_out = (J1_q[3] $ J1L7) & B1L1;
J1_q[3] = DFFEA(J1_q[3]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L9 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT at LC5_C7
--operation mode is clrb_cntr

J1L9 = CARRY(J1_q[3] & J1L7);


--J1_q[2] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[2] at LC4_C7
--operation mode is clrb_cntr

J1_q[2]_lut_out = (J1_q[2] $ J1L5) & B1L1;
J1_q[2] = DFFEA(J1_q[2]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L7 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT at LC4_C7
--operation mode is clrb_cntr

J1L7 = CARRY(J1_q[2] & J1L5);


--J1_q[0] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[0] at LC2_C7
--operation mode is clrb_cntr

J1_q[0]_lut_out = (!J1_q[0]) & B1L1;
J1_q[0] = DFFEA(J1_q[0]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L3 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC2_C7
--operation mode is clrb_cntr

J1L3 = CARRY(J1_q[0]);


--B1L7 is fdiv:inst|LessThan~111 at LC1_C7
--operation mode is normal

B1L7 = !J1_q[1] # !J1_q[3] # !J1_q[2] # !J1_q[0];


--J1_q[22] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22] at LC8_C11
--operation mode is clrb_cntr

J1_q[22]_lut_out = (J1_q[22] $ J1L54) & B1L1;
J1_q[22] = DFFEA(J1_q[22]_lut_out, GLOBAL(Clock_8MHz), , , , , );


--J1_q[21] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[21] at LC7_C11
--operation mode is clrb_cntr

J1_q[21]_lut_out = (J1_q[21] $ J1L34) & B1L1;
J1_q[21] = DFFEA(J1_q[21]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L54 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[21]~COUT at LC7_C11
--operation mode is clrb_cntr

J1L54 = CARRY(J1_q[21] & J1L34);


--J1_q[20] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[20] at LC6_C11
--operation mode is clrb_cntr

J1_q[20]_lut_out = (J1_q[20] $ J1L14) & B1L1;
J1_q[20] = DFFEA(J1_q[20]_lut_out, GLOBAL(Clock_8MHz), , , , , );

--J1L34 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT at LC6_C11
--operation mode is clrb_cntr

J1L34 = CARRY(J1_q[20] & J1L14);


--B1L2 is fdiv:inst|CNT~252 at LC4_C10
--operation mode is normal

B1L2 = !J1_q[20] & !J1_q[21] & !J1_q[22] & !Reset;


--B1L1 is fdiv:inst|CNT~46 at LC3_C10
--operation mode is normal

B1L1 = B1L6 & B1L5 & B1L2 & B1L7;


--C1L1 is counter_16_bits:inst1|LessThan~170 at LC5_A2
--operation mode is normal

C1L1 = !J2_q[0] # !J2_q[1] # !J2_q[2] # !J2_q[3];


--C1L2 is counter_16_bits:inst1|LessThan~171 at LC2_A1
--operation mode is normal

C1L2 = !J2_q[4] # !J2_q[5] # !J2_q[6] # !J2_q[7];


--C1L3 is counter_16_bits:inst1|LessThan~172 at LC2_A7
--operation mode is normal

C1L3 = !J2_q[8] # !J2_q[9] # !J2_q[10] # !J2_q[11];


--C1L4 is counter_16_bits:inst1|LessThan~173 at LC6_A2
--operation mode is normal

C1L4 = !J2_q[12] # !J2_q[13] # !J2_q[14] # !J2_q[15];


--C1L5 is counter_16_bits:inst1|LessThan~174 at LC2_A2
--operation mode is normal

C1L5 = C1L4 # C1L3 # C1L2 # C1L1;


--N6_cs_buffer[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC8_A16
--operation mode is arithmetic

N6_cs_buffer[6] = E1_second_pulse_out[6] $ Acceleration[6] $ N6_cout[5];

--N6_cout[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] at LC8_A16
--operation mode is arithmetic

N6_cout[6] = CARRY(E1_second_pulse_out[6] & Acceleration[6] # N6_cout[5] # !E1_second_pulse_out[6] & Acceleration[6] & N6_cout[5]);


--N3_cs_buffer[7] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC8_A19
--operation mode is arithmetic

N3_cs_buffer[7] = E1_second_pulse_out[6] $ Acceleration[6] $ N3_cout[6];

--N3_cout[7] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] at LC8_A19
--operation mode is arithmetic

N3_cout[7] = CARRY(E1_second_pulse_out[6] & N3_cout[6] # !Acceleration[6] # !E1_second_pulse_out[6] & !Acceleration[6] & N3_cout[6]);


--N6_cs_buffer[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC7_A16
--operation mode is arithmetic

N6_cs_buffer[5] = E1_second_pulse_out[5] $ Acceleration[5] $ N6_cout[4];

--N6_cout[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] at LC7_A16
--operation mode is arithmetic

N6_cout[5] = CARRY(E1_second_pulse_out[5] & Acceleration[5] # N6_cout[4] # !E1_second_pulse_out[5] & Acceleration[5] & N6_cout[4]);


--N3_cs_buffer[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC7_A19
--operation mode is arithmetic

N3_cs_buffer[6] = E1_second_pulse_out[5] $ Acceleration[5] $ N3_cout[5];

--N3_cout[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] at LC7_A19
--operation mode is arithmetic

N3_cout[6] = CARRY(E1_second_pulse_out[5] & N3_cout[5] # !Acceleration[5] # !E1_second_pulse_out[5] & !Acceleration[5] & N3_cout[5]);


--N6_cs_buffer[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC6_A16
--operation mode is arithmetic

N6_cs_buffer[4] = E1_second_pulse_out[4] $ Acceleration[4] $ N6_cout[3];

--N6_cout[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] at LC6_A16
--operation mode is arithmetic

N6_cout[4] = CARRY(E1_second_pulse_out[4] & Acceleration[4] # N6_cout[3] # !E1_second_pulse_out[4] & Acceleration[4] & N6_cout[3]);


--N3_cs_buffer[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC6_A19
--operation mode is arithmetic

N3_cs_buffer[5] = E1_second_pulse_out[4] $ Acceleration[4] $ N3_cout[4];

--N3_cout[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] at LC6_A19
--operation mode is arithmetic

N3_cout[5] = CARRY(E1_second_pulse_out[4] & N3_cout[4] # !Acceleration[4] # !E1_second_pulse_out[4] & !Acceleration[4] & N3_cout[4]);


--N6_cs_buffer[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC5_A16
--operation mode is arithmetic

N6_cs_buffer[3] = E1_second_pulse_out[3] $ Acceleration[3] $ N6_cout[2];

--N6_cout[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] at LC5_A16
--operation mode is arithmetic

N6_cout[3] = CARRY(E1_second_pulse_out[3] & Acceleration[3] # N6_cout[2] # !E1_second_pulse_out[3] & Acceleration[3] & N6_cout[2]);


--N3_cs_buffer[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC5_A19
--operation mode is arithmetic

N3_cs_buffer[4] = E1_second_pulse_out[3] $ Acceleration[3] $ N3_cout[3];

--N3_cout[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] at LC5_A19
--operation mode is arithmetic

N3_cout[4] = CARRY(E1_second_pulse_out[3] & N3_cout[3] # !Acceleration[3] # !E1_second_pulse_out[3] & !Acceleration[3] & N3_cout[3]);


--N6_cs_buffer[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC4_A16
--operation mode is arithmetic

N6_cs_buffer[2] = E1_second_pulse_out[2] $ Acceleration[2] $ N6_cout[1];

--N6_cout[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] at LC4_A16
--operation mode is arithmetic

N6_cout[2] = CARRY(E1_second_pulse_out[2] & Acceleration[2] # N6_cout[1] # !E1_second_pulse_out[2] & Acceleration[2] & N6_cout[1]);


--N3_cs_buffer[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC4_A19
--operation mode is arithmetic

N3_cs_buffer[3] = E1_second_pulse_out[2] $ Acceleration[2] $ N3_cout[2];

--N3_cout[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] at LC4_A19
--operation mode is arithmetic

N3_cout[3] = CARRY(E1_second_pulse_out[2] & N3_cout[2] # !Acceleration[2] # !E1_second_pulse_out[2] & !Acceleration[2] & N3_cout[2]);


--N6_cs_buffer[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC3_A16
--operation mode is arithmetic

N6_cs_buffer[1] = E1_second_pulse_out[1] $ Acceleration[1] $ N6_cout[0];

--N6_cout[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] at LC3_A16
--operation mode is arithmetic

N6_cout[1] = CARRY(E1_second_pulse_out[1] & Acceleration[1] # N6_cout[0] # !E1_second_pulse_out[1] & Acceleration[1] & N6_cout[0]);


--N3_cs_buffer[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC3_A19
--operation mode is arithmetic

N3_cs_buffer[2] = E1_second_pulse_out[1] $ Acceleration[1] $ N3_cout[1];

--N3_cout[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] at LC3_A19
--operation mode is arithmetic

N3_cout[2] = CARRY(E1_second_pulse_out[1] & N3_cout[1] # !Acceleration[1] # !E1_second_pulse_out[1] & !Acceleration[1] & N3_cout[1]);


--N3_cs_buffer[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC2_A19
--operation mode is arithmetic

N3_cs_buffer[1] = Acceleration[0] $ E1_second_pulse_out[0];

--N3_cout[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] at LC2_A19
--operation mode is arithmetic

N3_cout[1] = CARRY(E1_second_pulse_out[0] # !Acceleration[0]);


--N6_cs_buffer[0] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] at LC2_A16
--operation mode is arithmetic

N6_cs_buffer[0] = Acceleration[0] $ E1_second_pulse_out[0];

--N6_cout[0] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[0] at LC2_A16
--operation mode is arithmetic

N6_cout[0] = CARRY(Acceleration[0] & E1_second_pulse_out[0]);


--F1L24 is pulse_sum:inst4|pulse_out~131 at LC4_A12
--operation mode is normal

F1L24 = !F1_pulse_1[7] & !F1_pulse_1[8] & !F1_pulse_1[9] & !F1_pulse_1[10];


--F1L34 is pulse_sum:inst4|pulse_out~133 at LC5_A12
--operation mode is normal

F1L34 = (!F1_pulse_1[11] & !F1_pulse_1[12] & !F1_pulse_1[13] & !F1_pulse_1[14]) & CASCADE(F1L24);


--J3_q[8] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] at LC1_B5
--operation mode is clrb_cntr

J3_q[8]_lut_out = (J3_q[8] $ (A1L04 & J3L71)) & A1L93;
J3_q[8] = DFFEA(J3_q[8]_lut_out, GLOBAL(F1L93), , , A1L04, , );

--J3L91 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT at LC1_B5
--operation mode is clrb_cntr

J3L91 = CARRY(J3_q[8] & J3L71);


--J3_q[16] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] at LC1_B7
--operation mode is clrb_cntr

J3_q[16]_lut_out = (J3_q[16] $ (A1L04 & J3L33)) & A1L93;
J3_q[16] = DFFEA(J3_q[16]_lut_out, GLOBAL(F1L93), , , A1L04, , );

--J3L53 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT at LC1_B7
--operation mode is clrb_cntr

J3L53 = CARRY(J3_q[16] & J3L33);


--J3_q[9] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9] at LC2_B5
--operation mode is clrb_cntr

J3_q[9]_lut_out = (J3_q[9] $ (A1L04 & J3L91)) & A1L93;
J3_q[9] = DFFEA(J3_q[9]_lut_out, GLOBAL(F1L93), , , A1L04, , );

--J3L12 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT at LC2_B5
--operation mode is clrb_cntr

J3L12 = CARRY(J3_q[9] & J3L91);