📄 main.map.rpt
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; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 16 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sum_control:inst5|lpm_add_sub:Add0 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH ; 24 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_cch ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: second_pulse_latch:inst3|lpm_add_sub:Add1 ;
+------------------------+-------------+-----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-----------------------------------------------------+
; LPM_WIDTH ; 17 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_kjh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: second_pulse_latch:inst3|lpm_add_sub:Add0 ;
+------------------------+-------------+-----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-----------------------------------------------------+
; LPM_WIDTH ; 16 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_jjh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon May 26 19:42:40 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off main -c main
Info: Found 1 design units, including 1 entities, in source file counter_16_bits.v
Info: Found entity 1: counter_16_bits
Info: Found 1 design units, including 1 entities, in source file fdiv.v
Info: Found entity 1: fdiv
Info: Found 1 design units, including 1 entities, in source file pulse_16.v
Info: Found entity 1: pulse_16
Info: Found 1 design units, including 1 entities, in source file pulse_sum.v
Info: Found entity 1: pulse_sum
Info: Found 1 design units, including 1 entities, in source file second_pulse_latch.v
Info: Found entity 1: second_pulse_latch
Info: Found 1 design units, including 1 entities, in source file sum_control.v
Info: Found entity 1: sum_control
Info: Found 1 design units, including 1 entities, in source file main.bdf
Info: Found entity 1: main
Info: Elaborating entity "main" for the top level hierarchy
Info: Elaborating entity "sum_control" for hierarchy "sum_control:inst5"
Info: Elaborating entity "pulse_sum" for hierarchy "pulse_sum:inst4"
Warning (10240): Verilog HDL Always Construct warning at pulse_sum.v(20): inferring latch(es) for variable "cnt", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for "cnt[3]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for "cnt[2]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for "cnt[1]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(18): inferred latch for "cnt[0]"
Warning (10240): Verilog HDL Always Construct warning at pulse_sum.v(20): inferring latch(es) for variable "pulse_1", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[14]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[13]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[12]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[11]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[10]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[9]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[8]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[7]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[6]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[5]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[4]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[3]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[2]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[1]"
Info (10041): Verilog HDL or VHDL info at pulse_sum.v(22): inferred latch for "pulse_1[0]"
Warning (10030): Tied undriven net "pulse_1[15]" at pulse_sum.v(17) to 0
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