main.tan.rpt

是一些很好的FPGA设计实例

; Worst-case tco               ; N/A                                      ; None          ; 15.300 ns                        ; sum_control:inst5|out_control                                                         ; Pulse_Wave                                                                            ; Reset      ; --         ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 7.000 ns                         ; Reset                                                                                 ; Pulse_Wave                                                                            ; --         ; --         ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 5.900 ns                         ; Reset                                                                                 ; sum_control:inst5|out_control                                                         ; --         ; Reset      ; 0            ;
; Clock Setup: 'Reset'         ; N/A                                      ; None          ; 93.46 MHz ( period = 10.700 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset      ; 0            ;
; Clock Setup: 'Clock_8MHz'    ; N/A                                      ; None          ; 192.31 MHz ( period = 5.200 ns ) ; second_pulse_latch:inst3|second_pulse_out[0]                                          ; second_pulse_latch:inst3|second_pulse_out[14]                                         ; Clock_8MHz ; Clock_8MHz ; 0            ;
; Clock Hold: 'Reset'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset      ; 325          ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                       ;                                                                                       ;            ;            ; 325          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K10TC100-1      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Reset           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; Clock_8MHz      ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Reset'                                                                                                                                                                                                                                                                                                                                                                      ;