pulse_16.v

是一些很好的FPGA设计实例

module pulse_16(
				Reset,
				counter_data,
				pulse_16_out
				);
output [15:0] pulse_16_out;
input  Reset;
input  [15:0] counter_data;

reg [15:0] pulse_16_out;

always @(Reset,counter_data,pulse_16_out)
begin
  if(Reset == 1'b1)
    pulse_16_out <= 16'b0;
  else
  begin
    if(counter_data[0] == 1'b1)
      pulse_16_out[15] <= 1'b1;
    else
      pulse_16_out[15] <= 1'b0;

    if(counter_data[1:0] == 2'b10)
      pulse_16_out[14] <= 1'b1;
    else
      pulse_16_out[14] <= 1'b0;

    if(counter_data[2:0] == 3'b100)
      pulse_16_out[13] <= 1'b1;
    else
      pulse_16_out[13] <= 1'b0;

    if(counter_data[3:0] == 4'b1000)
      pulse_16_out[12] <= 1'b1;
    else
      pulse_16_out[12] <= 1'b0;

    if(counter_data[4:0] == 5'b10000)
      pulse_16_out[11] <= 1'b1;
    else
      pulse_16_out[11] <= 1'b0;

    if(counter_data[5:0] == 6'b100000)
      pulse_16_out[10] <= 1'b1;
    else
      pulse_16_out[10] <= 1'b0;

    if(counter_data[6:0] == 7'b1000000)
      pulse_16_out[9] <= 1'b1;
    else
      pulse_16_out[9] <= 1'b0;

    if(counter_data[7:0] == 8'b10000000)
      pulse_16_out[8] <= 1'b1;
    else
      pulse_16_out[8] <= 1'b0;

    if(counter_data[8:0] == 9'b100000000)
      pulse_16_out[7] <= 1'b1;
    else
      pulse_16_out[7] <= 1'b0;

    if(counter_data[9:0] == 10'b1000000000)
      pulse_16_out[6] <= 1'b1;
    else
      pulse_16_out[6] <= 1'b0;

    if(counter_data[10:0] == 11'b10000000000)
      pulse_16_out[5] <= 1'b1;
    else
      pulse_16_out[5] <= 1'b0;

    if(counter_data[11:0] == 12'b100000000000)
      pulse_16_out[4] <= 1'b1;
    else
      pulse_16_out[4] <= 1'b0;

    if(counter_data[12:0] == 13'b1000000000000)
      pulse_16_out[3] <= 1'b1;
    else
      pulse_16_out[3] <= 1'b0;

    if(counter_data[13:0] == 14'b10000000000000)
      pulse_16_out[2] <= 1'b1;
    else
      pulse_16_out[2] <= 1'b0;

    if(counter_data[14:0] == 15'b100000000000000)
      pulse_16_out[1] <= 1'b1;
    else
      pulse_16_out[1] <= 1'b0;

    if(counter_data[15:0] == 16'b1000000000000000)
      pulse_16_out[0] <= 1'b1;
    else
      pulse_16_out[0] <= 1'b0;

  end

end

endmodule