main.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 33.78 MHz 29.6 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 33.78 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 29.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register register " "Info: + Longest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC209 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC209; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.600 ns) 5.900 ns gate_control:inst3\|wire_2 2 REG LC211 24 " "Info: 2: + IC(3.300 ns) + CELL(2.600 ns) = 5.900 ns; Loc. = LC211; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 44.07 % ) " "Info: Total cell delay = 2.600 ns ( 44.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 55.93 % ) " "Info: Total interconnect delay = 3.300 ns ( 55.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.300ns } { 0.000ns 2.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.700 ns - Smallest " "Info: - Smallest clock skew is -6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 13.100 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_6 12 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_6; Fanout = 12; CLK Node = 'SW1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW1 } "NODE_NAME" } } { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.900 ns) 7.200 ns gate_control:inst3\|fref~126 2 COMB LOOP LC218 4 " "Info: 2: + IC(0.000 ns) + CELL(6.900 ns) = 7.200 ns; Loc. = LC218; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC218 " "Info: Loc. = LC218; Node \"gate_control:inst3\|fref~126\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.900 ns" { SW1 gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.100 ns gate_control:inst3\|wire_2 3 REG LC211 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.100 ns; Loc. = LC211; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.100 ns ( 77.10 % ) " "Info: Total cell delay = 10.100 ns ( 77.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 22.90 % ) " "Info: Total interconnect delay = 3.000 ns ( 22.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.100 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.100 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.900ns 2.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 19.800 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 19.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_6 12 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_6; Fanout = 12; CLK Node = 'SW1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW1 } "NODE_NAME" } } { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 7.200 ns gate_control:inst3\|fref~114 2 COMB LC208 3 " "Info: 2: + IC(3.200 ns) + CELL(3.700 ns) = 7.200 ns; Loc. = LC208; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.900 ns" { SW1 gate_control:inst3|fref~114 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 13.900 ns gate_control:inst3\|fref~126 3 COMB LOOP LC218 4 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.900 ns; Loc. = LC218; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC218 " "Info: Loc. = LC218; Node \"gate_control:inst3\|fref~126\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 19.800 ns gate_control:inst3\|wire_1 4 REG LC209 114 " "Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.800 ns; Loc. = LC209; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns ( 68.69 % ) " "Info: Total cell delay = 13.600 ns ( 68.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.200 ns ( 31.31 % ) " "Info: Total interconnect delay = 6.200 ns ( 31.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.800 ns" { SW1 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.800 ns" { SW1 SW1~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.200ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.100 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.100 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.900ns 2.900ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.800 ns" { SW1 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.800 ns" { SW1 SW1~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.200ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.300ns } { 0.000ns 2.600ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.100 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.100 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.900ns 2.900ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.800 ns" { SW1 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.800 ns" { SW1 SW1~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.200ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 33.78 MHz 29.6 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 33.78 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 29.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register register " "Info: + Longest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC209 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC209; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.600 ns) 5.900 ns gate_control:inst3\|wire_2 2 REG LC211 24 " "Info: 2: + IC(3.300 ns) + CELL(2.600 ns) = 5.900 ns; Loc. = LC211; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 44.07 % ) " "Info: Total cell delay = 2.600 ns ( 44.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 55.93 % ) " "Info: Total interconnect delay = 3.300 ns ( 55.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.300ns } { 0.000ns 2.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.700 ns - Smallest " "Info: - Smallest clock skew is -6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 13.100 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_17 16 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'SW2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW2 } "NODE_NAME" } } { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.900 ns) 7.200 ns gate_control:inst3\|fref~126 2 COMB LOOP LC218 4 " "Info: 2: + IC(0.000 ns) + CELL(6.900 ns) = 7.200 ns; Loc. = LC218; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC218 " "Info: Loc. = LC218; Node \"gate_control:inst3\|fref~126\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.900 ns" { SW2 gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.100 ns gate_control:inst3\|wire_2 3 REG LC211 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.100 ns; Loc. = LC211; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.100 ns ( 77.10 % ) " "Info: Total cell delay = 10.100 ns ( 77.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 22.90 % ) " "Info: Total interconnect delay = 3.000 ns ( 22.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.100 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.900ns 2.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 19.800 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 19.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_17 16 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'SW2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW2 } "NODE_NAME" } } { "main.bdf" "" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 7.200 ns gate_control:inst3\|fref~114 2 COMB LC208 3 " "Info: 2: + IC(3.200 ns) + CELL(3.700 ns) = 7.200 ns; Loc. = LC208; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.900 ns" { SW2 gate_control:inst3|fref~114 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 13.900 ns gate_control:inst3\|fref~126 3 COMB LOOP LC218 4 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.900 ns; Loc. = LC218; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC218 " "Info: Loc. = LC218; Node \"gate_control:inst3\|fref~126\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 19.800 ns gate_control:inst3\|wire_1 4 REG LC209 114 " "Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.800 ns; Loc. = LC209; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns ( 68.69 % ) " "Info: Total cell delay = 13.600 ns ( 68.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.200 ns ( 31.31 % ) " "Info: Total interconnect delay = 6.200 ns ( 31.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.800 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.800 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.200ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.100 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.900ns 2.900ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.800 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.800 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.200ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 21 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.900 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.900 ns" { gate_control:inst3|wire_1 gate_control:ins