main.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dp_s100hz gate_control.v(12) " "Info (10041): Verilog HDL or VHDL info at gate_control.v(12): inferred latch for \"dp_s100hz\"" {  } { { "gate_control.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/gate_control.v" 12 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fdiv fdiv:inst1 " "Info: Elaborating entity \"fdiv\" for hierarchy \"fdiv:inst1\"" {  } { { "main.bdf" "inst1" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 328 -48 48 456 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispdecoder dispdecoder:inst5 " "Info: Elaborating entity \"dispdecoder\" for hierarchy \"dispdecoder:inst5\"" {  } { { "main.bdf" "inst5" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 224 496 696 480 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "dispdecoder.v(24) " "Warning (10101): Verilog HDL unsupported feature warning at dispdecoder.v(24): Initial Construct is not supported and will be ignored" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 24 0 0 } }  } 0 10101 "Verilog HDL unsupported feature warning at %1!s!: Initial Construct is not supported and will be ignored" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "data_out dispdecoder.v(29) " "Warning (10240): Verilog HDL Always Construct warning at dispdecoder.v(29): inferring latch(es) for variable \"data_out\", which holds its previous value in one or more paths through the always construct" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_out\[6\] dispdecoder.v(31) " "Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for \"data_out\[6\]\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_out\[5\] dispdecoder.v(31) " "Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for \"data_out\[5\]\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_out\[4\] dispdecoder.v(31) " "Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for \"data_out\[4\]\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_out\[3\] dispdecoder.v(31) " "Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for \"data_out\[3\]\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_out\[2\] dispdecoder.v(31) " "Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for \"data_out\[2\]\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_out\[1\] dispdecoder.v(31) " "Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for \"data_out\[1\]\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_out\[0\] dispdecoder.v(31) " "Info (10041): Verilog HDL or VHDL info at dispdecoder.v(31): inferred latch for \"data_out\[0\]\"" {  } { { "dispdecoder.v" "" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/dispdecoder.v" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_mux data_mux:inst8 " "Info: Elaborating entity \"data_mux\" for hierarchy \"data_mux:inst8\"" {  } { { "main.bdf" "inst8" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 16 528 696 176 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "flip_latch flip_latch:inst2 " "Info: Elaborating entity \"flip_latch\" for hierarchy \"flip_latch:inst2\"" {  } { { "main.bdf" "inst2" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 0 336 472 160 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispselect dispselect:inst7 " "Info: Elaborating entity \"dispselect\" for hierarchy \"dispselect:inst7\"" {  } { { "main.bdf" "inst7" { Schematic "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.bdf" { { 376 80 232 472 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "10 " "Info: Inferred 10 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter:inst\|Q5\[0\]~176 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter:inst\|Q5\[0\]~176\"" {  } { { "counter.v" "Q5\[0\]~176" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 77 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter:inst\|Q0\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter:inst\|Q0\[0\]~4\"" {  } { { "counter.v" "Q0\[0\]~4" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 77 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter:inst\|Q1\[0\]~128 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter:inst\|Q1\[0\]~128\"" {  } { { "counter.v" "Q1\[0\]~128" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 77 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter:inst\|Q2\[0\]~140 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter:inst\|Q2\[0\]~140\"" {  } { { "counter.v" "Q2\[0\]~140" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 77 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter:inst\|Q3\[0\]~152 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter:inst\|Q3\[0\]~152\"" {  } { { "counter.v" "Q3\[0\]~152" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 77 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "counter:inst\|Q4\[0\]~164 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"counter:inst\|Q4\[0\]~164\"" {  } { { "counter.v" "Q4\[0\]~164" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/counter.v" 77 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "fdiv:inst1\|cnt1\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"fdiv:inst1\|cnt1\[0\]~32\"" {  } { { "fdiv.v" "cnt1\[0\]~32" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 22 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "fdiv:inst1\|cnt2\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"fdiv:inst1\|cnt2\[0\]~32\"" {  } { { "fdiv.v" "cnt2\[0\]~32" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 37 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "fdiv:inst1\|cnt4\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"fdiv:inst1\|cnt4\[0\]~32\"" {  } { { "fdiv.v" "cnt4\[0\]~32" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 67 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "fdiv:inst1\|cnt3\[0\]~32 32 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: \"fdiv:inst1\|cnt3\[0\]~32\"" {  } { { "fdiv.v" "cnt3\[0\]~32" { Text "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/fdiv.v" 52 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "counter:inst\|lpm_counter:Q5_rtl_0 " "Info: Elaborated megafunction instantiation \"counter:inst\|lpm_counter:Q5_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "counter:inst\|lpm_counter:Q0_rtl_1 " "Info: Elaborated megafunction instantiation \"counter:inst\|lpm_counter:Q0_rtl_1\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fdiv:inst1\|lpm_counter:cnt1_rtl_6 " "Info: Elaborated megafunction instantiation \"fdiv:inst1\|lpm_counter:cnt1_rtl_6\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "Clock " "Info: Promoted clock signal driven by pin \"Clock\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "F_in " "Info: Promoted clock signal driven by pin \"F_in\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "Clock " "Info: Promoted clock signal driven by pin \"Clock\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "F_in " "Info: Promoted clock signal driven by pin \"F_in\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "299 " "Info: Implemented 299 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "250 " "Info: Implemented 250 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "29 " "Info: Implemented 29 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 23 09:51:12 2008 " "Info: Processing ended: Fri May 23 09:51:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.map.smsg " "Info: Generated suppressed messages file E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/数字频率计/main/main.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}