block1.sim.vwf

是一些很好的FPGA设计实例

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 1000000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("b")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("a")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("so")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("co")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("b")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 180.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 200.0;
		LEVEL 0 FOR 999999140.0;
	}
}

TRANSITION_LIST("a")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 200.0;
		LEVEL 0 FOR 80.0;
		LEVEL 1 FOR 140.0;
		LEVEL 0 FOR 188722400.0;
		LEVEL 1 FOR 15360.0;
		LEVEL 0 FOR 15360.0;
		LEVEL 1 FOR 25600.0;
		LEVEL 0 FOR 10240.0;
		LEVEL 1 FOR 30720.0;
		LEVEL 0 FOR 15360.0;
		LEVEL 1 FOR 51200.0;
		LEVEL 0 FOR 811112960.0;
	}
}

TRANSITION_LIST("so")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 128.4;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 0.2;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 99.8;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 20.2;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 119.8;
		LEVEL 1 FOR 40.2;
		LEVEL 0 FOR 39.8;
		LEVEL 1 FOR 0.2;
		LEVEL 0 FOR 139.8;
		LEVEL 1 FOR 60.2;
		LEVEL 0 FOR 188722339.8;
		LEVEL 1 FOR 15360.0;
		LEVEL 0 FOR 15360.0;
		LEVEL 1 FOR 25600.0;
		LEVEL 0 FOR 10240.0;
		LEVEL 1 FOR 30720.0;
		LEVEL 0 FOR 15360.0;
		LEVEL 1 FOR 51200.0;
		LEVEL 0 FOR 811112951.6;
	}
}

TRANSITION_LIST("co")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 128.3;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 0.2;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 99.8;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 20.2;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 119.8;
		LEVEL 0 FOR 80.2;
		LEVEL 1 FOR 139.8;
		LEVEL 0 FOR 999999191.7;
	}
}

DISPLAY_LINE
{
	CHANNEL = "co";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "so";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "a";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "b";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 0;
	MASTER = TRUE;
}
;