full_multi.map.summary

来自「是一些很好的FPGA设计实例」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Thu Mar 22 13:51:11 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : full_multi
Top-level Entity Name : full_multi
Family : ACEX1K
Total logic elements : 45
Total pins : 19
Total memory bits : 0
Total PLLs : 0