i_love_u.tan.rpt

是一些很好的FPGA设计实例

Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Mar 30 21:50:10 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off I_love_u -c I_love_u
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 67.57 MHz between source register "a[1]" and destination register "q[1]~reg0" (period= 14.8 ns)
    Info: + Longest register to register delay is 13.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_D32; Fanout = 3; REG Node = 'a[1]'
        Info: 2: + IC(0.900 ns) + CELL(0.500 ns) = 1.400 ns; Loc. = LC2_D29; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]'
        Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 1.500 ns; Loc. = LC3_D29; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 1.600 ns; Loc. = LC4_D29; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 1.700 ns; Loc. = LC5_D29; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 1.800 ns; Loc. = LC6_D29; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 7: + IC(0.000 ns) + CELL(0.100 ns) = 1.900 ns; Loc. = LC7_D29; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 2.000 ns; Loc. = LC8_D29; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7]'
        Info: 9: + IC(0.400 ns) + CELL(0.100 ns) = 2.500 ns; Loc. = LC1_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8]'
        Info: 10: + IC(0.000 ns) + CELL(0.100 ns) = 2.600 ns; Loc. = LC2_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9]'
        Info: 11: + IC(0.000 ns) + CELL(0.100 ns) = 2.700 ns; Loc. = LC3_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10]'
        Info: 12: + IC(0.000 ns) + CELL(0.100 ns) = 2.800 ns; Loc. = LC4_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[11]'
        Info: 13: + IC(0.000 ns) + CELL(0.100 ns) = 2.900 ns; Loc. = LC5_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[12]'
        Info: 14: + IC(0.000 ns) + CELL(0.100 ns) = 3.000 ns; Loc. = LC6_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[13]'
        Info: 15: + IC(0.000 ns) + CELL(0.100 ns) = 3.100 ns; Loc. = LC7_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[14]'
        Info: 16: + IC(0.000 ns) + CELL(0.100 ns) = 3.200 ns; Loc. = LC8_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[15]'
        Info: 17: + IC(0.400 ns) + CELL(0.100 ns) = 3.700 ns; Loc. = LC1_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[16]'
        Info: 18: + IC(0.000 ns) + CELL(0.100 ns) = 3.800 ns; Loc. = LC2_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[17]'
        Info: 19: + IC(0.000 ns) + CELL(0.100 ns) = 3.900 ns; Loc. = LC3_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[18]'
        Info: 20: + IC(0.000 ns) + CELL(0.100 ns) = 4.000 ns; Loc. = LC4_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[19]'
        Info: 21: + IC(0.000 ns) + CELL(0.100 ns) = 4.100 ns; Loc. = LC5_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[20]'
        Info: 22: + IC(0.000 ns) + CELL(0.100 ns) = 4.200 ns; Loc. = LC6_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[21]'
        Info: 23: + IC(0.000 ns) + CELL(0.100 ns) = 4.300 ns; Loc. = LC7_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[22]'
        Info: 24: + IC(0.000 ns) + CELL(0.100 ns) = 4.400 ns; Loc. = LC8_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[23]'
        Info: 25: + IC(0.400 ns) + CELL(0.100 ns) = 4.900 ns; Loc. = LC1_D35; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[24]'
        Info: 26: + IC(0.000 ns) + CELL(0.100 ns) = 5.000 ns; Loc. = LC2_D35; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[25]'
        Info: 27: + IC(0.000 ns) + CELL(0.100 ns) = 5.100 ns; Loc. = LC3_D35; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[26]'
        Info: 28: + IC(0.000 ns) + CELL(0.100 ns) = 5.200 ns; Loc. = LC4_D35; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[27]'
        Info: 29: + IC(0.000 ns) + CELL(0.100 ns) = 5.300 ns; Loc. = LC5_D35; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[28]'
        Info: 30: + IC(0.000 ns) + CELL(0.100 ns) = 5.400 ns; Loc. = LC6_D35; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[29]'
        Info: 31: + IC(0.000 ns) + CELL(1.000 ns) = 6.400 ns; Loc. = LC7_D35; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[30]'
        Info: 32: + IC(0.700 ns) + CELL(1.100 ns) = 8.200 ns; Loc. = LC4_D36; Fanout = 1; COMB Node = 'Equal1~334'
        Info: 33: + IC(0.200 ns) + CELL(0.900 ns) = 9.300 ns; Loc. = LC1_D36; Fanout = 13; COMB Node = 'Equal1~340'
        Info: 34: + IC(2.200 ns) + CELL(0.900 ns) = 12.400 ns; Loc. = LC6_D2; Fanout = 5; COMB Node = 'Equal2~54'
        Info: 35: + IC(0.700 ns) + CELL(0.700 ns) = 13.800 ns; Loc. = LC7_D1; Fanout = 1; REG Node = 'q[1]~reg0'
        Info: Total cell delay = 7.900 ns ( 57.25 % )
        Info: Total interconnect delay = 5.900 ns ( 42.75 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 48; CLK Node = 'clk'
            Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC7_D1; Fanout = 1; REG Node = 'q[1]~reg0'
            Info: Total cell delay = 1.500 ns ( 83.33 % )
            Info: Total interconnect delay = 0.300 ns ( 16.67 % )
        Info: - Longest clock path from clock "clk" to source register is 1.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 48; CLK Node = 'clk'
            Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC8_D32; Fanout = 3; REG Node = 'a[1]'
            Info: Total cell delay = 1.500 ns ( 83.33 % )
            Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "clk" to destination pin "q[15]" through register "q[15]~reg0" is 9.300 ns
    Info: + Longest clock path from clock "clk" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 48; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC4_D2; Fanout = 1; REG Node = 'q[15]~reg0'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_D2; Fanout = 1; REG Node = 'q[15]~reg0'
        Info: 2: + IC(2.500 ns) + CELL(4.600 ns) = 7.100 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'q[15]'
        Info: Total cell delay = 4.600 ns ( 64.79 % )
        Info: Total interconnect delay = 2.500 ns ( 35.21 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Mar 30 21:50:11 2007
    Info: Elapsed time: 00:00:01