i_love_u.map.summary

来自「是一些很好的FPGA设计实例」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Fri Mar 30 21:49:52 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : I_love_u
Top-level Entity Name : I_love_u
Family : ACEX1K
Total logic elements : 91
Total pins : 17
Total memory bits : 0
Total PLLs : 0