mult_99.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 09 02:58:01 2007 " "Info: Processing started: Fri Feb 09 02:58:01 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mult_99 -c mult_99 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mult_99 -c mult_99" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/ym/text7/mult99.bdf " "Warning: Can't analyze file -- file C:/altera/ym/text7/mult99.bdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mult_99.bdf 1 1 " "Warning: Using design file mult_99.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mult_99 " "Info: Found entity 1: mult_99" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mult_99 " "Info: Elaborating entity \"mult_99\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "LPM_FILE mult99.mif " "Warning: Can't find a definition for parameter LPM_FILE -- assuming mult99.mif was intended to be a quoted string" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 0 344 456 96 "inst" "" } } } }  } 0 0 "Can't find a definition for parameter %1!s! -- assuming %2!s! was intended to be a quoted string" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/7493.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/7493.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7493 " "Info: Found entity 1: 7493" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7493 7493:inst39 " "Info: Elaborating entity \"7493\" for hierarchy \"7493:inst39\"" {  } { { "mult_99.bdf" "inst39" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 656 -272 -152 768 "inst39" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7493:inst39 " "Info: Elaborated megafunction instantiation \"7493:inst39\"" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 656 -272 -152 768 "inst39" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/74153M.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/74153M.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74153M " "Info: Found entity 1: 74153M" {  } { { "74153M.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74153M.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74153M 74153M:inst12 " "Info: Elaborating entity \"74153M\" for hierarchy \"74153M:inst12\"" {  } { { "mult_99.bdf" "inst12" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 488 920 1064 592 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74153M:inst12 " "Info: Elaborated megafunction instantiation \"74153M:inst12\"" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 488 920 1064 592 "inst12" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/74248.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/74248.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74248 " "Info: Found entity 1: 74248" {  } { { "74248.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74248.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74248 74248:inst5 " "Info: Elaborating entity \"74248\" for hierarchy \"74248:inst5\"" {  } { { "mult_99.bdf" "inst5" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 264 -104 8 424 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74248:inst5 " "Info: Elaborated megafunction instantiation \"74248:inst5\"" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 264 -104 8 424 "inst5" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/megafunctions/LPM_ROM.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/megafunctions/LPM_ROM.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 41 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM LPM_ROM:inst " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"LPM_ROM:inst\"" {  } { { "mult_99.bdf" "inst" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 0 344 456 96 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "LPM_ROM:inst " "Info: Elaborated megafunction instantiation \"LPM_ROM:inst\"" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 0 344 456 96 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altrom.tdf" 75 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom LPM_ROM:inst\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"LPM_ROM:inst\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "LPM_ROM:inst\|altrom:srom LPM_ROM:inst " "Info: Elaborated megafunction instantiation \"LPM_ROM:inst\|altrom:srom\", which is child of megafunction instantiation \"LPM_ROM:inst\"" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 52 3 0 } } { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 0 344 456 96 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "LPM_ROM:inst " "Info: Instantiated megafunction \"LPM_ROM:inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_ADDRESS_CONTROL REGISTERED " "Info: Parameter \"LPM_ADDRESS_CONTROL\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE mult99.mif " "Info: Parameter \"LPM_FILE\" = \"mult99.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 8 " "Info: Parameter \"LPM_WIDTHAD\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 0 344 456 96 "inst" "" } } } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[2\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[2\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[1\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[1\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[0\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[0\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[3\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[3\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[6\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[6\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[5\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[5\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[4\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[4\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "lpm_rom:inst\|otri\[7\] " "Warning: Converting TRI node \"lpm_rom:inst\|otri\[7\]\" that feeds logic to an OR gate" {  } { { "LPM_ROM.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SEL2 GND " "Warning: Pin \"SEL2\" stuck at GND" {  } { { "mult_99.bdf" "" { Schematic "C:/altera/ym/text7/mult_99.bdf" { { 832 32 208 848 "SEL2" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "86 " "Info: Implemented 86 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "59 " "Info: Implemented 59 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 09 02:58:07 2007 " "Info: Processing ended: Fri Feb 09 02:58:07 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}