mult_99.fit.summary

来自「是一些很好的FPGA设计实例」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Fri Feb 09 02:58:13 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : mult_99
Top-level Entity Name : mult_99
Family : ACEX1K
Device : EP1K30QC208-2
Timing Models : Final
Total logic elements : 60 / 1,728 ( 3 % )
Total pins : 19 / 147 ( 13 % )
Total memory bits : 2,048 / 24,576 ( 8 % )
Total PLLs : 0 / 1 ( 0 % )