mult_99.tan.rpt

是一些很好的FPGA设计实例

; N/A   ; None              ; 13.700 ns       ; address[0] ; E  ;
; N/A   ; None              ; 13.700 ns       ; address[2] ; E  ;
; N/A   ; None              ; 13.700 ns       ; address[1] ; C  ;
; N/A   ; None              ; 13.600 ns       ; address[3] ; C  ;
; N/A   ; None              ; 13.500 ns       ; address[1] ; E  ;
; N/A   ; None              ; 13.400 ns       ; address[4] ; D  ;
; N/A   ; None              ; 13.300 ns       ; address[4] ; G  ;
+-------+-------------------+-----------------+------------+----+


+---------------------------------------------------------------------------------------------------------+
; th                                                                                                      ;
+---------------+-------------+-----------+------------+---------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                                    ; To Clock ;
+---------------+-------------+-----------+------------+---------------------------------------+----------+
; N/A           ; None        ; -4.800 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra0 ; clk      ;
; N/A           ; None        ; -4.800 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra0 ; clk      ;
; N/A           ; None        ; -4.800 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra0 ; clk      ;
; N/A           ; None        ; -4.800 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra0 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra3 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra3 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra3 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra3 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra2 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra2 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra2 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra2 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[1] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra1 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra0 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra0 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra0 ; clk      ;
; N/A           ; None        ; -4.900 ns ; address[0] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra0 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[4] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra4 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra3 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra3 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra3 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[3] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra3 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra2 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra2 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra2 ; clk      ;
; N/A           ; None        ; -5.000 ns ; address[2] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra2 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra5 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra5 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra5 ; clk      ;
; N/A           ; None        ; -5.700 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra5 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[7] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra7 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[0]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[7]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[5]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[6] ; lpm_rom:inst|altrom:srom|q[6]~reg_ra6 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[3]~reg_ra5 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[1]~reg_ra5 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[4]~reg_ra5 ; clk      ;
; N/A           ; None        ; -5.800 ns ; address[5] ; lpm_rom:inst|altrom:srom|q[2]~reg_ra5 ; clk      ;
+---------------+-------------+-----------+------------+---------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Feb 09 02:58:17 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mult_99 -c mult_99
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "7493:inst39|16" as buffer
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "7493:inst39|15" and destination register "7493:inst39|15"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F31; Fanout = 13; REG Node = '7493:inst39|15'
            Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC3_F31; Fanout = 13; REG Node = '7493:inst39|15'
            Info: Total cell delay = 0.500 ns ( 71.43 % )
            Info: Total interconnect delay = 0.200 ns ( 28.57 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 5.700 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'
                Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C17; Fanout = 30; REG Node = '7493:inst39|16'
                Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 5.700 ns; Loc. = LC3_F31; Fanout = 13; REG Node = '