tube_control.tan.rpt

是一些很好的FPGA设计实例

; Slack ; Required tco ; Actual tco ; From          ; To   ; From Clock ;
+-------+--------------+------------+---------------+------+------------+
; N/A   ; None         ; 11.700 ns  ; 7493:inst7|14 ; F    ; clk        ;
; N/A   ; None         ; 11.600 ns  ; 7493:inst7|13 ; F    ; clk        ;
; N/A   ; None         ; 11.600 ns  ; 7493:inst7|14 ; E    ; clk        ;
; N/A   ; None         ; 11.600 ns  ; 7493:inst7|15 ; E    ; clk        ;
; N/A   ; None         ; 11.400 ns  ; 7493:inst7|15 ; F    ; clk        ;
; N/A   ; None         ; 11.000 ns  ; 7493:inst7|14 ; A    ; clk        ;
; N/A   ; None         ; 11.000 ns  ; 7493:inst7|15 ; A    ; clk        ;
; N/A   ; None         ; 11.000 ns  ; 7493:inst7|13 ; G    ; clk        ;
; N/A   ; None         ; 11.000 ns  ; 7493:inst7|13 ; D    ; clk        ;
; N/A   ; None         ; 11.000 ns  ; 7493:inst7|14 ; B    ; clk        ;
; N/A   ; None         ; 11.000 ns  ; 7493:inst7|15 ; B    ; clk        ;
; N/A   ; None         ; 10.900 ns  ; 7493:inst7|14 ; G    ; clk        ;
; N/A   ; None         ; 10.900 ns  ; 7493:inst7|15 ; G    ; clk        ;
; N/A   ; None         ; 10.900 ns  ; 7493:inst7|15 ; D    ; clk        ;
; N/A   ; None         ; 10.900 ns  ; 7493:inst7|14 ; C    ; clk        ;
; N/A   ; None         ; 10.900 ns  ; 7493:inst7|15 ; C    ; clk        ;
; N/A   ; None         ; 10.800 ns  ; 7493:inst7|13 ; A    ; clk        ;
; N/A   ; None         ; 10.800 ns  ; 7493:inst7|13 ; B    ; clk        ;
; N/A   ; None         ; 10.700 ns  ; 7493:inst7|14 ; D    ; clk        ;
; N/A   ; None         ; 10.700 ns  ; 7493:inst7|13 ; C    ; clk        ;
; N/A   ; None         ; 10.500 ns  ; 7493:inst7|16 ; A    ; clk        ;
; N/A   ; None         ; 10.500 ns  ; 7493:inst7|16 ; B    ; clk        ;
; N/A   ; None         ; 10.400 ns  ; 7493:inst7|16 ; C    ; clk        ;
; N/A   ; None         ; 10.300 ns  ; 7493:inst7|16 ; D    ; clk        ;
; N/A   ; None         ; 10.100 ns  ; 7493:inst7|16 ; G    ; clk        ;
; N/A   ; None         ; 9.600 ns   ; 7493:inst7|16 ; F    ; clk        ;
; N/A   ; None         ; 9.400 ns   ; 7493:inst7|16 ; E    ; clk        ;
; N/A   ; None         ; 9.100 ns   ; 7493:inst2|14 ; sel2 ; 32768hz    ;
; N/A   ; None         ; 9.100 ns   ; 7493:inst2|15 ; sel1 ; 32768hz    ;
; N/A   ; None         ; 7.700 ns   ; 7493:inst2|16 ; sel0 ; 32768hz    ;
+-------+--------------+------------+---------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jan 19 23:37:00 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tube_control -c tube_control
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "32768hz" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "7493:inst2|16" as buffer
    Info: Detected ripple clock "7493:inst7|16" as buffer
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "7493:inst7|15" and destination register "7493:inst7|14"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_E28; Fanout = 10; REG Node = '7493:inst7|15'
            Info: 2: + IC(0.200 ns) + CELL(0.800 ns) = 1.000 ns; Loc. = LC4_E28; Fanout = 9; REG Node = '7493:inst7|14'
            Info: Total cell delay = 0.800 ns ( 80.00 % )
            Info: Total interconnect delay = 0.200 ns ( 20.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.100 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_E30; Fanout = 11; REG Node = '7493:inst7|16'
                Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC4_E28; Fanout = 9; REG Node = '7493:inst7|14'
                Info: Total cell delay = 1.900 ns ( 61.29 % )
                Info: Total interconnect delay = 1.200 ns ( 38.71 % )
            Info: - Longest clock path from clock "clk" to source register is 3.100 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_E30; Fanout = 11; REG Node = '7493:inst7|16'
                Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC6_E28; Fanout = 10; REG Node = '7493:inst7|15'
                Info: Total cell delay = 1.900 ns ( 61.29 % )
                Info: Total interconnect delay = 1.200 ns ( 38.71 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: Clock "32768hz" Internal fmax is restricted to 200.0 MHz between source register "7493:inst2|15" and destination register "7493:inst2|14"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A24; Fanout = 3; REG Node = '7493:inst2|15'
            Info: 2: + IC(0.200 ns) + CELL(0.800 ns) = 1.000 ns; Loc. = LC4_A24; Fanout = 2; REG Node = '7493:inst2|14'
            Info: Total cell delay = 0.800 ns ( 80.00 % )
            Info: Total interconnect delay = 0.200 ns ( 20.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "32768hz" to destination register is 3.100 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_78; Fanout = 1; CLK Node = '32768hz'
                Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_A33; Fanout = 4; REG Node = '7493:inst2|16'
                Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC4_A24; Fanout = 2; REG Node = '7493:inst2|14'
                Info: Total cell delay = 1.900 ns ( 61.29 % )
                Info: Total interconnect delay = 1.200 ns ( 38.71 % )
            Info: - Longest clock path from clock "32768hz" to source register is 3.100 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_78; Fanout = 1; CLK Node = '32768hz'
                Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_A33; Fanout = 4; REG Node = '7493:inst2|16'
                Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC3_A24; Fanout = 3; REG Node = '7493:inst2|15'
                Info: Total cell delay = 1.900 ns ( 61.29 % )
                Info: Total interconnect delay = 1.200 ns ( 38.71 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "clk" to destination pin "F" through register "7493:inst7|14" is 11.700 ns
    Info: + Longest clock path from clock "clk" to source register is 3.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_E30; Fanout = 11; REG Node = '7493:inst7|16'
        Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC4_E28; Fanout = 9; REG Node = '7493:inst7|14'
        Info: Total cell delay = 1.900 ns ( 61.29 % )
        Info: Total interconnect delay = 1.200 ns ( 38.71 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 8.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_E28; Fanout = 9; REG Node = '7493:inst7|14'
        Info: 2: + IC(0.900 ns) + CELL(1.200 ns) = 2.100 ns; Loc. = LC7_E30; Fanout = 1; COMB Node = '74248:inst1|89~70'
        Info: 3: + IC(1.500 ns) + CELL(4.600 ns) = 8.200 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'F'
        Info: Total cell delay = 5.800 ns ( 70.73 % )
        Info: Total interconnect delay = 2.400 ns ( 29.27 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Jan 19 23:37:01 2007
    Info: Elapsed time: 00:00:01