tube_control.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 19 23:36:51 2007 " "Info: Processing started: Fri Jan 19 23:36:51 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off tube_control -c tube_control " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tube_control -c tube_control" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tube_control.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file tube_control.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 tube_control " "Info: Found entity 1: tube_control" {  } { { "tube_control.bdf" "" { Schematic "C:/altera/ym/text3/tube_control.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "tube_control " "Info: Elaborating entity \"tube_control\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/74248.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/74248.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74248 " "Info: Found entity 1: 74248" {  } { { "74248.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74248.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74248 74248:inst1 " "Info: Elaborating entity \"74248\" for hierarchy \"74248:inst1\"" {  } { { "tube_control.bdf" "inst1" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 56 296 408 216 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74248:inst1 " "Info: Elaborated megafunction instantiation \"74248:inst1\"" {  } { { "tube_control.bdf" "" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 56 296 408 216 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/7493.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/7493.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7493 " "Info: Found entity 1: 7493" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7493 7493:inst7 " "Info: Elaborating entity \"7493\" for hierarchy \"7493:inst7\"" {  } { { "tube_control.bdf" "inst7" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 56 80 200 168 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7493:inst7 " "Info: Elaborated megafunction instantiation \"7493:inst7\"" {  } { { "tube_control.bdf" "" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 56 80 200 168 "inst7" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "28 " "Info: Implemented 28 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "15 " "Info: Implemented 15 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 19 23:36:52 2007 " "Info: Processing ended: Fri Jan 19 23:36:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}