tube_control.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "32768hz register register 7493:inst2\|15 7493:inst2\|14 200.0 MHz Internal " "Info: Clock \"32768hz\" Internal fmax is restricted to 200.0 MHz between source register \"7493:inst2\|15\" and destination register \"7493:inst2\|14\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.000 ns + Longest register register " "Info: + Longest register to register delay is 1.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:inst2\|15 1 REG LC3_A24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A24; Fanout = 3; REG Node = '7493:inst2\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst2|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.800 ns) 1.000 ns 7493:inst2\|14 2 REG LC4_A24 2 " "Info: 2: + IC(0.200 ns) + CELL(0.800 ns) = 1.000 ns; Loc. = LC4_A24; Fanout = 2; REG Node = '7493:inst2\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { 7493:inst2|15 7493:inst2|14 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 80.00 % ) " "Info: Total cell delay = 0.800 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 20.00 % ) " "Info: Total interconnect delay = 0.200 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { 7493:inst2|15 7493:inst2|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.000 ns" { 7493:inst2|15 7493:inst2|14 } { 0.000ns 0.200ns } { 0.000ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "32768hz destination 3.100 ns + Shortest register " "Info: + Shortest clock path from clock \"32768hz\" to destination register is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns 32768hz 1 CLK PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_78; Fanout = 1; CLK Node = '32768hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 32768hz } "NODE_NAME" } } { "tube_control.bdf" "" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 360 -248 -80 376 "32768hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst2\|16 2 REG LC1_A33 4 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_A33; Fanout = 4; REG Node = '7493:inst2\|16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 32768hz 7493:inst2|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.000 ns) 3.100 ns 7493:inst2\|14 3 REG LC4_A24 2 " "Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC4_A24; Fanout = 2; REG Node = '7493:inst2\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { 7493:inst2|16 7493:inst2|14 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 61.29 % ) " "Info: Total cell delay = 1.900 ns ( 61.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 38.71 % ) " "Info: Total interconnect delay = 1.200 ns ( 38.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 32768hz 7493:inst2|16 7493:inst2|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 32768hz 32768hz~out 7493:inst2|16 7493:inst2|14 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "32768hz source 3.100 ns - Longest register " "Info: - Longest clock path from clock \"32768hz\" to source register is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns 32768hz 1 CLK PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_78; Fanout = 1; CLK Node = '32768hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 32768hz } "NODE_NAME" } } { "tube_control.bdf" "" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 360 -248 -80 376 "32768hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst2\|16 2 REG LC1_A33 4 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_A33; Fanout = 4; REG Node = '7493:inst2\|16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 32768hz 7493:inst2|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.000 ns) 3.100 ns 7493:inst2\|15 3 REG LC3_A24 3 " "Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC3_A24; Fanout = 3; REG Node = '7493:inst2\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { 7493:inst2|16 7493:inst2|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 61.29 % ) " "Info: Total cell delay = 1.900 ns ( 61.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 38.71 % ) " "Info: Total interconnect delay = 1.200 ns ( 38.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 32768hz 7493:inst2|16 7493:inst2|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 32768hz 32768hz~out 7493:inst2|16 7493:inst2|15 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 32768hz 7493:inst2|16 7493:inst2|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 32768hz 32768hz~out 7493:inst2|16 7493:inst2|14 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 32768hz 7493:inst2|16 7493:inst2|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 32768hz 32768hz~out 7493:inst2|16 7493:inst2|15 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { 7493:inst2|15 7493:inst2|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.000 ns" { 7493:inst2|15 7493:inst2|14 } { 0.000ns 0.200ns } { 0.000ns 0.800ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 32768hz 7493:inst2|16 7493:inst2|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 32768hz 32768hz~out 7493:inst2|16 7493:inst2|14 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { 32768hz 7493:inst2|16 7493:inst2|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { 32768hz 32768hz~out 7493:inst2|16 7493:inst2|15 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst2|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { 7493:inst2|14 } {  } {  } } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk F 7493:inst7\|14 11.700 ns register " "Info: tco from clock \"clk\" to destination pin \"F\" through register \"7493:inst7\|14\" is 11.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_79 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "tube_control.bdf" "" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 120 -216 -48 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst7\|16 2 REG LC1_E30 11 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_E30; Fanout = 11; REG Node = '7493:inst7\|16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { clk 7493:inst7|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.000 ns) 3.100 ns 7493:inst7\|14 3 REG LC4_E28 9 " "Info: 3: + IC(0.900 ns) + CELL(0.000 ns) = 3.100 ns; Loc. = LC4_E28; Fanout = 9; REG Node = '7493:inst7\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { 7493:inst7|16 7493:inst7|14 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 61.29 % ) " "Info: Total cell delay = 1.900 ns ( 61.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 38.71 % ) " "Info: Total interconnect delay = 1.200 ns ( 38.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { clk 7493:inst7|16 7493:inst7|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { clk clk~out 7493:inst7|16 7493:inst7|14 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.200 ns + Longest register pin " "Info: + Longest register to pin delay is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:inst7\|14 1 REG LC4_E28 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_E28; Fanout = 9; REG Node = '7493:inst7\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst7|14 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.200 ns) 2.100 ns 74248:inst1\|89~70 2 COMB LC7_E30 1 " "Info: 2: + IC(0.900 ns) + CELL(1.200 ns) = 2.100 ns; Loc. = LC7_E30; Fanout = 1; COMB Node = '74248:inst1\|89~70'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { 7493:inst7|14 74248:inst1|89~70 } "NODE_NAME" } } { "74248.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74248.bdf" { { 816 848 912 888 "89" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(4.600 ns) 8.200 ns F 3 PIN PIN_15 0 " "Info: 3: + IC(1.500 ns) + CELL(4.600 ns) = 8.200 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'F'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.100 ns" { 74248:inst1|89~70 F } "NODE_NAME" } } { "tube_control.bdf" "" { Schematic "C:/altera/ym/text3/tube_control.bdf" { { 168 496 672 184 "F" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 70.73 % ) " "Info: Total cell delay = 5.800 ns ( 70.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 29.27 % ) " "Info: Total interconnect delay = 2.400 ns ( 29.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.200 ns" { 7493:inst7|14 74248:inst1|89~70 F } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.200 ns" { 7493:inst7|14 74248:inst1|89~70 F } { 0.000ns 0.900ns 1.500ns } { 0.000ns 1.200ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { clk 7493:inst7|16 7493:inst7|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.100 ns" { clk clk~out 7493:inst7|16 7493:inst7|14 } { 0.000ns 0.000ns 0.300ns 0.900ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.200 ns" { 7493:inst7|14 74248:inst1|89~70 F } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.200 ns" { 7493:inst7|14 74248:inst1|89~70 F } { 0.000ns 0.900ns 1.500ns } { 0.000ns 1.200ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 19 23:37:01 2007 " "Info: Processing ended: Fri Jan 19 23:37:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}