smdisplay.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_TH_RESULT" "74175:inst7\|15 D\[5\] clk 0.700 ns register " "Info: th for register \"74175:inst7\|15\" (data pin = \"D\[5\]\", clock pin = \"clk\") is 0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_79 32 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "smdisplay.bdf" "" { Schematic "C:/altera/ym/text8/smdisplay.bdf" { { 1408 -152 16 1424 "clk" "" } { 344 16 80 360 "clk" "" } { 520 16 80 536 "clk" "" } { 696 16 80 712 "clk" "" } { 872 16 80 888 "clk" "" } { 1048 16 80 1064 "clk" "" } { 1224 16 80 1240 "clk" "" } { 1400 16 80 1416 "clk" "" } { 168 56 80 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns 74175:inst7\|15 2 REG LC1_C2 9 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_C2; Fanout = 9; REG Node = '74175:inst7\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { clk 74175:inst7|15 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk 74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out 74175:inst7|15 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.000 ns + " "Info: + Micro hold delay of destination is 1.000 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns D\[5\] 1 PIN PIN_184 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_184; Fanout = 1; PIN Node = 'D\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } } { "smdisplay.bdf" "" { Schematic "C:/altera/ym/text8/smdisplay.bdf" { { 0 -104 64 16 "D\[31..0\]" "" } { 40 48 80 56 "D\[0\]" "" } { 56 48 80 72 "D\[1\]" "" } { 72 48 80 88 "D\[2\]" "" } { 88 48 80 104 "D\[3\]" "" } { 216 48 80 232 "D\[4\]" "" } { 232 48 80 248 "D\[5\]" "" } { 248 48 80 264 "D\[6\]" "" } { 264 48 80 280 "D\[7\]" "" } { 392 48 80 408 "D\[8\]" "" } { 408 48 80 424 "D\[9\]" "" } { 424 48 85 440 "D\[10\]" "" } { 440 48 85 456 "D\[11\]" "" } { 568 48 83 584 "D\[12\]" "" } { 584 48 85 600 "D\[13\]" "" } { 600 48 85 616 "D\[14\]" "" } { 616 48 85 632 "D\[15\]" "" } { 744 48 83 760 "D\[16\]" "" } { 760 48 85 776 "D\[17\]" "" } { 776 48 85 792 "D\[18\]" "" } { 792 48 85 808 "D\[19\]" "" } { 920 48 83 936 "D\[20\]" "" } { 936 48 85 952 "D\[21\]" "" } { 968 48 80 984 "D\[23\]" "" } { 952 48 85 968 "D\[22\]" "" } { 1096 48 83 1112 "D\[24\]" "" } { 1112 48 85 1128 "D\[25\]" "" } { 1128 48 85 1144 "D\[26\]" "" } { 1144 48 85 1160 "D\[27\]" "" } { 1272 48 83 1288 "D\[28\]" "" } { 1288 48 85 1304 "D\[29\]" "" } { 1304 48 85 1320 "D\[30\]" "" } { 1320 48 85 1336 "D\[31\]" "" } { -8 64 128 8 "D\[31..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.500 ns) 2.100 ns 74175:inst7\|15 2 REG LC1_C2 9 " "Info: 2: + IC(0.100 ns) + CELL(0.500 ns) = 2.100 ns; Loc. = LC1_C2; Fanout = 9; REG Node = '74175:inst7\|15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { D[5] 74175:inst7|15 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 184 352 416 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 95.24 % ) " "Info: Total cell delay = 2.000 ns ( 95.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns ( 4.76 % ) " "Info: Total interconnect delay = 0.100 ns ( 4.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { D[5] 74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.100 ns" { D[5] D[5]~out 74175:inst7|15 } { 0.000ns 0.000ns 0.100ns } { 0.000ns 1.500ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk 74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { clk clk~out 74175:inst7|15 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { D[5] 74175:inst7|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.100 ns" { D[5] D[5]~out 74175:inst7|15 } { 0.000ns 0.000ns 0.100ns } { 0.000ns 1.500ns 0.500ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 26 04:45:47 2007 " "Info: Processing ended: Mon Feb 26 04:45:47 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}