smdisplay.tan.rpt

是一些很好的FPGA设计实例

; N/A   ; None              ; 13.400 ns       ; C    ; OA   ;
; N/A   ; None              ; 13.200 ns       ; C    ; SEL2 ;
; N/A   ; None              ; 13.000 ns       ; B    ; SEL1 ;
; N/A   ; None              ; 12.900 ns       ; C    ; OG   ;
; N/A   ; None              ; 12.600 ns       ; A    ; SEL0 ;
+-------+-------------------+-----------------+------+------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+-------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To              ; To Clock ;
+---------------+-------------+-----------+-------+-----------------+----------+
; N/A           ; None        ; 0.700 ns  ; D[5]  ; 74175:inst7|15  ; clk      ;
; N/A           ; None        ; 0.600 ns  ; D[6]  ; 74175:inst7|14  ; clk      ;
; N/A           ; None        ; 0.600 ns  ; D[7]  ; 74175:inst7|13  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; D[11] ; 74175:inst12|13 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; D[4]  ; 74175:inst7|16  ; clk      ;
; N/A           ; None        ; -2.100 ns ; D[25] ; 74175:inst28|15 ; clk      ;
; N/A           ; None        ; -2.100 ns ; D[12] ; 74175:inst17|16 ; clk      ;
; N/A           ; None        ; -2.400 ns ; D[9]  ; 74175:inst12|15 ; clk      ;
; N/A           ; None        ; -2.500 ns ; D[19] ; 74175:inst22|13 ; clk      ;
; N/A           ; None        ; -2.700 ns ; D[21] ; 74175:inst27|15 ; clk      ;
; N/A           ; None        ; -2.800 ns ; D[30] ; 74175:inst29|14 ; clk      ;
; N/A           ; None        ; -2.800 ns ; D[13] ; 74175:inst17|15 ; clk      ;
; N/A           ; None        ; -2.900 ns ; D[18] ; 74175:inst22|14 ; clk      ;
; N/A           ; None        ; -2.900 ns ; D[27] ; 74175:inst28|13 ; clk      ;
; N/A           ; None        ; -2.900 ns ; D[8]  ; 74175:inst12|16 ; clk      ;
; N/A           ; None        ; -2.900 ns ; D[0]  ; 74175:inst|16   ; clk      ;
; N/A           ; None        ; -2.900 ns ; D[1]  ; 74175:inst|15   ; clk      ;
; N/A           ; None        ; -3.000 ns ; D[31] ; 74175:inst29|13 ; clk      ;
; N/A           ; None        ; -3.000 ns ; D[10] ; 74175:inst12|14 ; clk      ;
; N/A           ; None        ; -3.000 ns ; D[2]  ; 74175:inst|14   ; clk      ;
; N/A           ; None        ; -3.100 ns ; D[29] ; 74175:inst29|15 ; clk      ;
; N/A           ; None        ; -3.200 ns ; D[15] ; 74175:inst17|13 ; clk      ;
; N/A           ; None        ; -3.300 ns ; D[20] ; 74175:inst27|16 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[22] ; 74175:inst27|14 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[23] ; 74175:inst27|13 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[17] ; 74175:inst22|15 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[16] ; 74175:inst22|16 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[14] ; 74175:inst17|14 ; clk      ;
; N/A           ; None        ; -3.500 ns ; D[28] ; 74175:inst29|16 ; clk      ;
; N/A           ; None        ; -3.500 ns ; D[24] ; 74175:inst28|16 ; clk      ;
; N/A           ; None        ; -3.500 ns ; D[26] ; 74175:inst28|14 ; clk      ;
; N/A           ; None        ; -3.900 ns ; D[3]  ; 74175:inst|13   ; clk      ;
+---------------+-------------+-----------+-------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Feb 26 04:45:46 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off smdisplay -c smdisplay
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "74175:inst|13" (data pin = "D[3]", clock pin = "clk") is 5.500 ns
    Info: + Longest pin to register delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_56; Fanout = 1; PIN Node = 'D[3]'
        Info: 2: + IC(2.700 ns) + CELL(0.500 ns) = 6.700 ns; Loc. = LC2_C17; Fanout = 5; REG Node = '74175:inst|13'
        Info: Total cell delay = 4.000 ns ( 59.70 % )
        Info: Total interconnect delay = 2.700 ns ( 40.30 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_C17; Fanout = 5; REG Node = '74175:inst|13'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: tco from clock "clk" to destination pin "OB" through register "74175:inst17|16" is 18.700 ns
    Info: + Longest clock path from clock "clk" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC5_C35; Fanout = 9; REG Node = '74175:inst17|16'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 16.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C35; Fanout = 9; REG Node = '74175:inst17|16'
        Info: 2: + IC(2.200 ns) + CELL(0.900 ns) = 3.100 ns; Loc. = LC5_C9; Fanout = 1; COMB Node = '74151:inst26|f74151:sub|72~228'
        Info: 3: + IC(0.200 ns) + CELL(0.900 ns) = 4.200 ns; Loc. = LC4_C9; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|68~152'
        Info: 4: + IC(1.000 ns) + CELL(1.200 ns) = 6.400 ns; Loc. = LC7_C13; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|68~153'
        Info: 5: + IC(1.700 ns) + CELL(1.100 ns) = 9.200 ns; Loc. = LC6_C26; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|78~3'
        Info: 6: + IC(0.200 ns) + CELL(1.100 ns) = 10.500 ns; Loc. = LC7_C26; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|81~4'
        Info: 7: + IC(1.400 ns) + CELL(4.600 ns) = 16.500 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'OB'
        Info: Total cell delay = 9.800 ns ( 59.39 % )
        Info: Total interconnect delay = 6.700 ns ( 40.61 % )
Info: Longest tpd from source pin "A" to destination pin "OB" is 22.500 ns
    Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_45; Fanout = 67; PIN Node = 'A'
    Info: 2: + IC(4.800 ns) + CELL(1.100 ns) = 9.400 ns; Loc. = LC2_C2; Fanout = 3; COMB Node = '74151:inst6|f74151:sub|70~158'
    Info: 3: + IC(2.000 ns) + CELL(1.200 ns) = 12.600 ns; Loc. = LC6_C24; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|70~155'
    Info: 4: + IC(0.900 ns) + CELL(0.700 ns) = 14.200 ns; Loc. = LC1_C26; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|74~10'
    Info: 5: + IC(0.000 ns) + CELL(1.200 ns) = 15.400 ns; Loc. = LC2_C26; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|77~3'
    Info: 6: + IC(0.200 ns) + CELL(0.900 ns) = 16.500 ns; Loc. = LC7_C26; Fanout = 1; COMB Node = '74151:inst21|f74151:sub|81~4'
    Info: 7: + IC(1.400 ns) + CELL(4.600 ns) = 22.500 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'OB'
    Info: Total cell delay = 13.200 ns ( 58.67 % )
    Info: Total interconnect delay = 9.300 ns ( 41.33 % )
Info: th for register "74175:inst7|15" (data pin = "D[5]", clock pin = "clk") is 0.700 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_C2; Fanout = 9; REG Node = '74175:inst7|15'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.000 ns
    Info: - Shortest pin to register delay is 2.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_184; Fanout = 1; PIN Node = 'D[5]'
        Info: 2: + IC(0.100 ns) + CELL(0.500 ns) = 2.100 ns; Loc. = LC1_C2; Fanout = 9; REG Node = '74175:inst7|15'
        Info: Total cell delay = 2.000 ns ( 95.24 % )
        Info: Total interconnect delay = 0.100 ns ( 4.76 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Feb 26 04:45:47 2007
    Info: Elapsed time: 00:00:02