📄 count.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "EN register register 7493:inst1\|15 7493:inst1\|15 200.0 MHz Internal " "Info: Clock \"EN\" Internal fmax is restricted to 200.0 MHz between source register \"7493:inst1\|15\" and destination register \"7493:inst1\|15\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.700 ns + Longest register register " "Info: + Longest register to register delay is 0.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:inst1\|15 1 REG LC1_F11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1\|15'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.500 ns) 0.700 ns 7493:inst1\|15 2 REG LC1_F11 5 " "Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1\|15'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 7493:inst1|15 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 71.43 % ) " "Info: Total cell delay = 0.500 ns ( 71.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 28.57 % ) " "Info: Total interconnect delay = 0.200 ns ( 28.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 7493:inst1|15 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.700 ns" { 7493:inst1|15 7493:inst1|15 } { 0.000ns 0.200ns } { 0.000ns 0.500ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN destination 7.000 ns + Shortest register " "Info: + Shortest clock path from clock \"EN\" to destination register is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns EN 1 CLK PIN_182 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_182; Fanout = 1; CLK Node = 'EN'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 208 -128 40 224 "EN" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 2.900 ns inst9 2 COMB LC2_C16 1 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { EN inst9 } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 232 96 160 280 "inst9" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.400 ns) 3.500 ns 7493:inst1\|16 3 REG LC1_C16 6 " "Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.500 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { inst9 7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 7.000 ns 7493:inst1\|15 4 REG LC1_F11 5 " "Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1\|15'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 42.86 % ) " "Info: Total cell delay = 3.000 ns ( 42.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 57.14 % ) " "Info: Total interconnect delay = 4.000 ns ( 57.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN source 7.000 ns - Longest register " "Info: - Longest clock path from clock \"EN\" to source register is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns EN 1 CLK PIN_182 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_182; Fanout = 1; CLK Node = 'EN'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 208 -128 40 224 "EN" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 2.900 ns inst9 2 COMB LC2_C16 1 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { EN inst9 } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 232 96 160 280 "inst9" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.400 ns) 3.500 ns 7493:inst1\|16 3 REG LC1_C16 6 " "Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.500 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { inst9 7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 7.000 ns 7493:inst1\|15 4 REG LC1_F11 5 " "Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1\|15'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 42.86 % ) " "Info: Total cell delay = 3.000 ns ( 42.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 57.14 % ) " "Info: Total interconnect delay = 4.000 ns ( 57.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" { } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { 7493:inst1|15 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.700 ns" { 7493:inst1|15 7493:inst1|15 } { 0.000ns 0.200ns } { 0.000ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { 7493:inst1|15 } { } { } } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "EN Q\[0\] 7493:inst1\|15 14.300 ns register " "Info: tco from clock \"EN\" to destination pin \"Q\[0\]\" through register \"7493:inst1\|15\" is 14.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN source 7.000 ns + Longest register " "Info: + Longest clock path from clock \"EN\" to source register is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns EN 1 CLK PIN_182 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_182; Fanout = 1; CLK Node = 'EN'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 208 -128 40 224 "EN" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 2.900 ns inst9 2 COMB LC2_C16 1 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { EN inst9 } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 232 96 160 280 "inst9" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.400 ns) 3.500 ns 7493:inst1\|16 3 REG LC1_C16 6 " "Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.500 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { inst9 7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 7.000 ns 7493:inst1\|15 4 REG LC1_F11 5 " "Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1\|15'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 42.86 % ) " "Info: Total cell delay = 3.000 ns ( 42.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 57.14 % ) " "Info: Total interconnect delay = 4.000 ns ( 57.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" { } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns + Longest register pin " "Info: + Longest register to pin delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:inst1\|15 1 REG LC1_F11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1\|15'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.100 ns) 1.300 ns 74138:inst5\|15~32 2 COMB LC3_F11 1 " "Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC3_F11; Fanout = 1; COMB Node = '74138:inst5\|15~32'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { 7493:inst1|15 74138:inst5|15~32 } "NODE_NAME" } } { "74138.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74138.bdf" { { 16 568 632 88 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.600 ns) 6.900 ns Q\[0\] 3 PIN PIN_115 0 " "Info: 3: + IC(1.000 ns) + CELL(4.600 ns) = 6.900 ns; Loc. = PIN_115; Fanout = 0; PIN Node = 'Q\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { 74138:inst5|15~32 Q[0] } "NODE_NAME" } } { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 264 696 872 280 "Q\[3..0\]" "" } { 176 544 728 192 "Q\[0\]" "" } { 192 592 728 208 "Q\[1\]" "" } { 208 640 728 224 "Q\[2\]" "" } { 224 688 728 240 "Q\[3\]" "" } { 256 584 696 272 "Q\[3..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 82.61 % ) " "Info: Total cell delay = 5.700 ns ( 82.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 17.39 % ) " "Info: Total interconnect delay = 1.200 ns ( 17.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.900 ns" { 7493:inst1|15 74138:inst5|15~32 Q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.900 ns" { 7493:inst1|15 74138:inst5|15~32 Q[0] } { 0.000ns 0.200ns 1.000ns } { 0.000ns 1.100ns 4.600ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { EN inst9 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { EN EN~out inst9 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 0.200ns 3.500ns } { 0.000ns 1.500ns 1.100ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.900 ns" { 7493:inst1|15 74138:inst5|15~32 Q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.900 ns" { 7493:inst1|15 74138:inst5|15~32 Q[0] } { 0.000ns 0.200ns 1.000ns } { 0.000ns 1.100ns 4.600ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 16 23:57:20 2007 " "Info: Processing ended: Fri Feb 16 23:57:20 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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