count.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 16 23:57:09 2007 " "Info: Processing started: Fri Feb 16 23:57:09 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off COUNT -c COUNT " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off COUNT -c COUNT" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/ym/text9/COUNT1/COUNT1.bdf " "Warning: Can't analyze file -- file C:/altera/ym/text9/COUNT1/COUNT1.bdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "COUNT.bdf 1 1 " "Warning: Using design file COUNT.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 COUNT " "Info: Found entity 1: COUNT" {  } { { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "COUNT " "Info: Elaborating entity \"COUNT\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "C 74138 inst5 " "Warning: Port \"C\" of type 74138 and instance \"inst5\" is missing source signal" {  } { { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 168 376 496 328 "inst5" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus60/libraries/others/maxplus2/74138.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../quartus60/libraries/others/maxplus2/74138.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74138 " "Info: Found entity 1: 74138" {  } { { "74138.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74138.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74138 74138:inst5 " "Info: Elaborating entity \"74138\" for hierarchy \"74138:inst5\"" {  } { { "COUNT.bdf" "inst5" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 168 376 496 328 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74138:inst5 " "Info: Elaborated megafunction instantiation \"74138:inst5\"" {  } { { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 168 376 496 328 "inst5" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../quartus60/libraries/others/maxplus2/7493.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../quartus60/libraries/others/maxplus2/7493.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7493 " "Info: Found entity 1: 7493" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7493 7493:inst1 " "Info: Elaborating entity \"7493\" for hierarchy \"7493:inst1\"" {  } { { "COUNT.bdf" "inst1" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 184 192 312 296 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "7493:inst1 " "Info: Elaborated megafunction instantiation \"7493:inst1\"" {  } { { "COUNT.bdf" "" { Schematic "C:/altera/ym/text9/COUNT1/COUNT.bdf" { { 184 192 312 296 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "13 " "Info: Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 16 23:57:10 2007 " "Info: Processing ended: Fri Feb 16 23:57:10 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}