count.tan.rpt

是一些很好的FPGA设计实例

+-------+--------------+------------+---------------+------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To   ; From Clock ;
+-------+--------------+------------+---------------+------+------------+
; N/A   ; None         ; 14.300 ns  ; 7493:inst1|15 ; Q[0] ; EN         ;
; N/A   ; None         ; 14.300 ns  ; 7493:inst1|15 ; Q[2] ; EN         ;
; N/A   ; None         ; 14.200 ns  ; 7493:inst1|15 ; Q[3] ; EN         ;
; N/A   ; None         ; 14.100 ns  ; 7493:inst1|15 ; Q[0] ; clk        ;
; N/A   ; None         ; 14.100 ns  ; 7493:inst1|15 ; Q[1] ; EN         ;
; N/A   ; None         ; 14.100 ns  ; 7493:inst1|15 ; Q[2] ; clk        ;
; N/A   ; None         ; 14.000 ns  ; 7493:inst1|15 ; Q[3] ; clk        ;
; N/A   ; None         ; 13.900 ns  ; 7493:inst1|15 ; Q[1] ; clk        ;
; N/A   ; None         ; 11.900 ns  ; 7493:inst1|16 ; Q[1] ; EN         ;
; N/A   ; None         ; 11.700 ns  ; 7493:inst1|16 ; Q[0] ; EN         ;
; N/A   ; None         ; 11.700 ns  ; 7493:inst1|16 ; Q[1] ; clk        ;
; N/A   ; None         ; 11.700 ns  ; 7493:inst1|16 ; Q[2] ; EN         ;
; N/A   ; None         ; 11.600 ns  ; 7493:inst1|16 ; Q[3] ; EN         ;
; N/A   ; None         ; 11.500 ns  ; 7493:inst1|16 ; Q[0] ; clk        ;
; N/A   ; None         ; 11.500 ns  ; 7493:inst1|16 ; Q[2] ; clk        ;
; N/A   ; None         ; 11.400 ns  ; 7493:inst1|16 ; Q[3] ; clk        ;
+-------+--------------+------------+---------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Feb 16 23:57:19 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off COUNT -c COUNT
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "EN" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "inst9" as buffer
    Info: Detected ripple clock "7493:inst1|16" as buffer
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "7493:inst1|15" and destination register "7493:inst1|15"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
            Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
            Info: Total cell delay = 0.500 ns ( 71.43 % )
            Info: Total interconnect delay = 0.200 ns ( 28.57 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 6.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_78; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.300 ns) + CELL(0.900 ns) = 2.700 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'
                Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.300 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1|16'
                Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 6.800 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
                Info: Total cell delay = 2.800 ns ( 41.18 % )
                Info: Total interconnect delay = 4.000 ns ( 58.82 % )
            Info: - Longest clock path from clock "clk" to source register is 6.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_78; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.300 ns) + CELL(0.900 ns) = 2.700 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'
                Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.300 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1|16'
                Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 6.800 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
                Info: Total cell delay = 2.800 ns ( 41.18 % )
                Info: Total interconnect delay = 4.000 ns ( 58.82 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: Clock "EN" Internal fmax is restricted to 200.0 MHz between source register "7493:inst1|15" and destination register "7493:inst1|15"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
            Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 0.700 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
            Info: Total cell delay = 0.500 ns ( 71.43 % )
            Info: Total interconnect delay = 0.200 ns ( 28.57 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "EN" to destination register is 7.000 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_182; Fanout = 1; CLK Node = 'EN'
                Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'
                Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.500 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1|16'
                Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
                Info: Total cell delay = 3.000 ns ( 42.86 % )
                Info: Total interconnect delay = 4.000 ns ( 57.14 % )
            Info: - Longest clock path from clock "EN" to source register is 7.000 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_182; Fanout = 1; CLK Node = 'EN'
                Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'
                Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.500 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1|16'
                Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
                Info: Total cell delay = 3.000 ns ( 42.86 % )
                Info: Total interconnect delay = 4.000 ns ( 57.14 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "EN" to destination pin "Q[0]" through register "7493:inst1|15" is 14.300 ns
    Info: + Longest clock path from clock "EN" to source register is 7.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_182; Fanout = 1; CLK Node = 'EN'
        Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 2.900 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'inst9'
        Info: 3: + IC(0.200 ns) + CELL(0.400 ns) = 3.500 ns; Loc. = LC1_C16; Fanout = 6; REG Node = '7493:inst1|16'
        Info: 4: + IC(3.500 ns) + CELL(0.000 ns) = 7.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
        Info: Total cell delay = 3.000 ns ( 42.86 % )
        Info: Total interconnect delay = 4.000 ns ( 57.14 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F11; Fanout = 5; REG Node = '7493:inst1|15'
        Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC3_F11; Fanout = 1; COMB Node = '74138:inst5|15~32'
        Info: 3: + IC(1.000 ns) + CELL(4.600 ns) = 6.900 ns; Loc. = PIN_115; Fanout = 0; PIN Node = 'Q[0]'
        Info: Total cell delay = 5.700 ns ( 82.61 % )
        Info: Total interconnect delay = 1.200 ns ( 17.39 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Feb 16 23:57:20 2007
    Info: Elapsed time: 00:00:02