control1.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 26 21:50:11 2007 " "Info: Processing started: Mon Feb 26 21:50:11 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CONTROL1 -c CONTROL1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CONTROL1 -c CONTROL1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CONTROL1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CONTROL1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CONTROL1 " "Info: Found entity 1: CONTROL1" {  } { { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CONTROL1 " "Info: Elaborating entity \"CONTROL1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN 74175 inst1 " "Warning: Port \"CLRN\" of type 74175 and instance \"inst1\" is missing source signal" {  } { { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 184 88 208 360 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "control.v(29) " "Warning (10273): Verilog HDL warning at control.v(29): extended using \"x\" or \"z\"" {  } { { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 29 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WSGN_SEARCH_FILE" "control.v 1 1 " "Warning: Using design file control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 control " "Info: Found entity 1: control" {  } { { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control control:inst " "Info: Elaborating entity \"control\" for hierarchy \"control:inst\"" {  } { { "CONTROL1.bdf" "inst" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 112 312 464 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_GENERIC_WARNING_WITH_LOC" "can't check case statement for completeness because the case expression has too many possible states control.v(21) " "Warning (10005): Verilog HDL or VHDL warning at control.v(21): can't check case statement for completeness because the case expression has too many possible states" {  } { { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 21 0 0 } }  } 0 10005 "Verilog HDL or VHDL warning at %2!s!: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/others/maxplus2/74175.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/others/maxplus2/74175.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74175 " "Info: Found entity 1: 74175" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74175 74175:inst1 " "Info: Elaborating entity \"74175\" for hierarchy \"74175:inst1\"" {  } { { "CONTROL1.bdf" "inst1" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 184 88 208 360 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74175:inst1 " "Info: Elaborated megafunction instantiation \"74175:inst1\"" {  } { { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 184 88 208 360 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"control:inst\|lpm_add_sub:Add0\"" {  } { { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 19 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}