control1.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_TH_RESULT" "74175:inst1\|14 dout\[2\] CLK 0.400 ns register " "Info: th for register \"74175:inst1\|14\" (data pin = \"dout\[2\]\", clock pin = \"CLK\") is 0.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.800 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns 74175:inst1\|14 2 REG LC2_A32 7 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_A32; Fanout = 7; REG Node = '74175:inst1\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { CLK 74175:inst1|14 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|14 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.000 ns + " "Info: + Micro hold delay of destination is 1.000 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns dout\[2\] 1 PIN PIN_183 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_183; Fanout = 1; PIN Node = 'dout\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dout[2] } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 56 -72 96 72 "dout\[3..0\]" "" } { 48 96 143 64 "dout\[3..0\]" "" } { 240 16 88 256 "dout\[3\]" "" } { 224 16 88 240 "dout\[2\]" "" } { 208 16 88 224 "dout\[1\]" "" } { 192 16 88 208 "dout\[0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.400 ns 74175:inst1\|14 2 REG LC2_A32 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.400 ns; Loc. = LC2_A32; Fanout = 7; REG Node = '74175:inst1\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { dout[2] 74175:inst1|14 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { dout[2] 74175:inst1|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { dout[2] dout[2]~out 74175:inst1|14 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 1.500ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|14 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { dout[2] 74175:inst1|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { dout[2] dout[2]~out 74175:inst1|14 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 1.500ns 0.500ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 26 21:50:27 2007 " "Info: Processing ended: Mon Feb 26 21:50:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}