control1.tan.qmsg

是一些很好的FPGA设计实例

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 146 " "Warning: Circuit may not operate. Detected 146 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "74175:inst1\|16 control:inst\|DATA\[8\] CLK 2.2 ns " "Info: Found hold time violation between source  pin or register \"74175:inst1\|16\" and destination pin or register \"control:inst\|DATA\[8\]\" for clock \"CLK\" (Hold time is 2.2 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.600 ns + Largest " "Info: + Largest clock skew is 3.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns inst2 2 REG LC1_D8 57 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_D8; Fanout = 57; REG Node = 'inst2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { CLK inst2 } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 72 152 216 152 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 5.400 ns control:inst\|DATA\[8\] 3 REG LC3_A32 2 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC3_A32; Fanout = 2; REG Node = 'control:inst\|DATA\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { inst2 control:inst|DATA[8] } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 35.19 % ) " "Info: Total cell delay = 1.900 ns ( 35.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 64.81 % ) " "Info: Total interconnect delay = 3.500 ns ( 64.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[8] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns 74175:inst1\|16 2 REG LC8_A32 7 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC8_A32; Fanout = 7; REG Node = '74175:inst1\|16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { CLK 74175:inst1|16 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|16 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[8] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|16 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns - " "Info: - Micro clock to output delay of source is 0.400 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.000 ns - Shortest register register " "Info: - Shortest register to register delay is 2.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74175:inst1\|16 1 REG LC8_A32 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A32; Fanout = 7; REG Node = '74175:inst1\|16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 74175:inst1|16 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.100 ns) 1.300 ns control:inst\|Selector15~12 2 COMB LC4_A32 1 " "Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC4_A32; Fanout = 1; COMB Node = 'control:inst\|Selector15~12'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { 74175:inst1|16 control:inst|Selector15~12 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.500 ns) 2.000 ns control:inst\|DATA\[8\] 3 REG LC3_A32 2 " "Info: 3: + IC(0.200 ns) + CELL(0.500 ns) = 2.000 ns; Loc. = LC3_A32; Fanout = 2; REG Node = 'control:inst\|DATA\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { control:inst|Selector15~12 control:inst|DATA[8] } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 80.00 % ) " "Info: Total cell delay = 1.600 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 20.00 % ) " "Info: Total interconnect delay = 0.400 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { 74175:inst1|16 control:inst|Selector15~12 control:inst|DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.000 ns" { 74175:inst1|16 control:inst|Selector15~12 control:inst|DATA[8] } { 0.000ns 0.200ns 0.200ns } { 0.000ns 1.100ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.000 ns + " "Info: + Micro hold delay of destination is 1.000 ns" {  } { { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 40 352 416 120 "16" "" } } } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[8] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|16 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|16 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { 74175:inst1|16 control:inst|Selector15~12 control:inst|DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.000 ns" { 74175:inst1|16 control:inst|Selector15~12 control:inst|DATA[8] } { 0.000ns 0.200ns 0.200ns } { 0.000ns 1.100ns 0.500ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "inst2 en CLK 4.000 ns register " "Info: tsu for register \"inst2\" (data pin = \"en\", clock pin = \"CLK\") is 4.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest pin register " "Info: + Longest pin to register delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns en 1 PIN PIN_125 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_125; Fanout = 1; PIN Node = 'en'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 88 -56 112 104 "en" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.500 ns) 5.200 ns inst2 2 REG LC1_D8 57 " "Info: 2: + IC(1.200 ns) + CELL(0.500 ns) = 5.200 ns; Loc. = LC1_D8; Fanout = 57; REG Node = 'inst2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { en inst2 } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 72 152 216 152 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 76.92 % ) " "Info: Total cell delay = 4.000 ns ( 76.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 23.08 % ) " "Info: Total interconnect delay = 1.200 ns ( 23.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { en inst2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.200 ns" { en en~out inst2 } { 0.000ns 0.000ns 1.200ns } { 0.000ns 3.500ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 72 152 216 152 "inst2" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns inst2 2 REG LC1_D8 57 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_D8; Fanout = 57; REG Node = 'inst2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { CLK inst2 } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 72 152 216 152 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK inst2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out inst2 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { en inst2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.200 ns" { en en~out inst2 } { 0.000ns 0.000ns 1.200ns } { 0.000ns 3.500ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK inst2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out inst2 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DATA\[0\] control:inst\|DATA\[0\] 12.300 ns register " "Info: tco from clock \"CLK\" to destination pin \"DATA\[0\]\" through register \"control:inst\|DATA\[0\]\" is 12.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns inst2 2 REG LC1_D8 57 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_D8; Fanout = 57; REG Node = 'inst2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { CLK inst2 } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 72 152 216 152 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 5.400 ns control:inst\|DATA\[0\] 3 REG LC1_A29 2 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC1_A29; Fanout = 2; REG Node = 'control:inst\|DATA\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { inst2 control:inst|DATA[0] } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 35.19 % ) " "Info: Total cell delay = 1.900 ns ( 35.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 64.81 % ) " "Info: Total interconnect delay = 3.500 ns ( 64.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[0] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest register pin " "Info: + Longest register to pin delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:inst\|DATA\[0\] 1 REG LC1_A29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A29; Fanout = 2; REG Node = 'control:inst\|DATA\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { control:inst|DATA[0] } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(4.600 ns) 6.500 ns DATA\[0\] 2 PIN PIN_150 0 " "Info: 2: + IC(1.900 ns) + CELL(4.600 ns) = 6.500 ns; Loc. = PIN_150; Fanout = 0; PIN Node = 'DATA\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { control:inst|DATA[0] DATA[0] } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 136 488 664 152 "DATA\[23..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 70.77 % ) " "Info: Total cell delay = 4.600 ns ( 70.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 29.23 % ) " "Info: Total interconnect delay = 1.900 ns ( 29.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { control:inst|DATA[0] DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { control:inst|DATA[0] DATA[0] } { 0.000ns 1.900ns } { 0.000ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[0] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { control:inst|DATA[0] DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { control:inst|DATA[0] DATA[0] } { 0.000ns 1.900ns } { 0.000ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}