control1.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "inst2 " "Info: Detected ripple clock \"inst2\" as buffer" {  } { { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 72 152 216 152 "inst2" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register 74175:inst1\|14 register control:inst\|DATA\[22\] 52.63 MHz 19.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 52.63 MHz between source register \"74175:inst1\|14\" and destination register \"control:inst\|DATA\[22\]\" (period= 19.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.100 ns + Longest register register " "Info: + Longest register to register delay is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74175:inst1\|14 1 REG LC2_A32 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A32; Fanout = 7; REG Node = '74175:inst1\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 74175:inst1|14 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 1.400 ns control:inst\|Equal0~34 2 COMB LC5_A32 53 " "Info: 2: + IC(0.200 ns) + CELL(1.200 ns) = 1.400 ns; Loc. = LC5_A32; Fanout = 53; COMB Node = 'control:inst\|Equal0~34'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { 74175:inst1|14 control:inst|Equal0~34 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.500 ns) 3.300 ns control:inst\|Equal2~973 3 COMB LC2_A21 1 " "Info: 3: + IC(1.400 ns) + CELL(0.500 ns) = 3.300 ns; Loc. = LC2_A21; Fanout = 1; COMB Node = 'control:inst\|Equal2~973'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { control:inst|Equal0~34 control:inst|Equal2~973 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 4.500 ns control:inst\|Equal2~949 4 COMB LC3_A21 1 " "Info: 4: + IC(0.000 ns) + CELL(1.200 ns) = 4.500 ns; Loc. = LC3_A21; Fanout = 1; COMB Node = 'control:inst\|Equal2~949'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { control:inst|Equal2~973 control:inst|Equal2~949 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.700 ns) 6.200 ns control:inst\|Equal2~964 5 COMB LC7_A28 1 " "Info: 5: + IC(1.000 ns) + CELL(0.700 ns) = 6.200 ns; Loc. = LC7_A28; Fanout = 1; COMB Node = 'control:inst\|Equal2~964'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { control:inst|Equal2~949 control:inst|Equal2~964 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 7.400 ns control:inst\|Equal2~946 6 COMB LC8_A28 22 " "Info: 6: + IC(0.000 ns) + CELL(1.200 ns) = 7.400 ns; Loc. = LC8_A28; Fanout = 22; COMB Node = 'control:inst\|Equal2~946'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { control:inst|Equal2~964 control:inst|Equal2~946 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.100 ns) 9.500 ns control:inst\|Equal3~76 7 COMB LC8_A33 4 " "Info: 7: + IC(1.000 ns) + CELL(1.100 ns) = 9.500 ns; Loc. = LC8_A33; Fanout = 4; COMB Node = 'control:inst\|Equal3~76'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { control:inst|Equal2~946 control:inst|Equal3~76 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(1.100 ns) 11.400 ns control:inst\|Selector1~12 8 COMB LC1_A36 1 " "Info: 8: + IC(0.800 ns) + CELL(1.100 ns) = 11.400 ns; Loc. = LC1_A36; Fanout = 1; COMB Node = 'control:inst\|Selector1~12'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { control:inst|Equal3~76 control:inst|Selector1~12 } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.500 ns) 12.100 ns control:inst\|DATA\[22\] 9 REG LC5_A36 2 " "Info: 9: + IC(0.200 ns) + CELL(0.500 ns) = 12.100 ns; Loc. = LC5_A36; Fanout = 2; REG Node = 'control:inst\|DATA\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { control:inst|Selector1~12 control:inst|DATA[22] } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 61.98 % ) " "Info: Total cell delay = 7.500 ns ( 61.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 38.02 % ) " "Info: Total interconnect delay = 4.600 ns ( 38.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.100 ns" { 74175:inst1|14 control:inst|Equal0~34 control:inst|Equal2~973 control:inst|Equal2~949 control:inst|Equal2~964 control:inst|Equal2~946 control:inst|Equal3~76 control:inst|Selector1~12 control:inst|DATA[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.100 ns" { 74175:inst1|14 control:inst|Equal0~34 control:inst|Equal2~973 control:inst|Equal2~949 control:inst|Equal2~964 control:inst|Equal2~946 control:inst|Equal3~76 control:inst|Selector1~12 control:inst|DATA[22] } { 0.000ns 0.200ns 1.400ns 0.000ns 1.000ns 0.000ns 1.000ns 0.800ns 0.200ns } { 0.000ns 1.200ns 0.500ns 1.200ns 0.700ns 1.200ns 1.100ns 1.100ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.600 ns - Smallest " "Info: - Smallest clock skew is 3.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns inst2 2 REG LC1_D8 57 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_D8; Fanout = 57; REG Node = 'inst2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { CLK inst2 } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 72 152 216 152 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 5.400 ns control:inst\|DATA\[22\] 3 REG LC5_A36 2 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC5_A36; Fanout = 2; REG Node = 'control:inst\|DATA\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { inst2 control:inst|DATA[22] } "NODE_NAME" } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 35.19 % ) " "Info: Total cell delay = 1.900 ns ( 35.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 64.81 % ) " "Info: Total interconnect delay = 3.500 ns ( 64.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[22] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 5 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CONTROL1.bdf" "" { Schematic "C:/altera/ym/text9/keyboard/control/CONTROL1.bdf" { { 328 -208 -40 344 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns 74175:inst1\|14 2 REG LC2_A32 7 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_A32; Fanout = 7; REG Node = '74175:inst1\|14'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.300 ns" { CLK 74175:inst1|14 } "NODE_NAME" } } { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 83.33 % ) " "Info: Total cell delay = 1.500 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|14 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[22] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|14 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "74175.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74175.bdf" { { 344 352 416 424 "14" "" } } } } { "control.v" "" { Text "C:/altera/ym/text9/keyboard/control/control.v" 31 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.100 ns" { 74175:inst1|14 control:inst|Equal0~34 control:inst|Equal2~973 control:inst|Equal2~949 control:inst|Equal2~964 control:inst|Equal2~946 control:inst|Equal3~76 control:inst|Selector1~12 control:inst|DATA[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.100 ns" { 74175:inst1|14 control:inst|Equal0~34 control:inst|Equal2~973 control:inst|Equal2~949 control:inst|Equal2~964 control:inst|Equal2~946 control:inst|Equal3~76 control:inst|Selector1~12 control:inst|DATA[22] } { 0.000ns 0.200ns 1.400ns 0.000ns 1.000ns 0.000ns 1.000ns 0.800ns 0.200ns } { 0.000ns 1.200ns 0.500ns 1.200ns 0.700ns 1.200ns 1.100ns 1.100ns 0.500ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK inst2 control:inst|DATA[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out inst2 control:inst|DATA[22] } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { CLK 74175:inst1|14 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { CLK CLK~out 74175:inst1|14 } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}