control1.tan.summary

是一些很好的FPGA设计实例

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.000 ns
From           : en
To             : inst2
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.300 ns
From           : control:inst|DATA[16]
To             : DATA[16]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.400 ns
From           : dout[1]
To             : 74175:inst1|15
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 52.63 MHz ( period = 19.000 ns )
From           : 74175:inst1|14
To             : control:inst|DATA[4]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Hold: 'CLK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : 74175:inst1|16
To             : control:inst|DATA[8]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 146

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 146

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