control1.sim.rpt

是一些很好的FPGA设计实例

+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      24.10 % ;
; Total nodes checked                                 ; 188          ;
; Total output ports checked                          ; 195          ;
; Total output ports with complete 1/0-value coverage ; 47           ;
; Total output ports with no 1/0-value coverage       ; 122          ;
; Total output ports with no 1-value coverage         ; 122          ;
; Total output ports with no 0-value coverage         ; 148          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                  ; Output Port Name                                                                           ; Output Port Type ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; |CONTROL1|control:inst|i[0]                                                                ; |CONTROL1|control:inst|i[0]                                                                ; data_out0        ;
; |CONTROL1|control:inst|i[0]                                                                ; |CONTROL1|control:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |CONTROL1|74175:inst1|14                                                                   ; |CONTROL1|74175:inst1|14                                                                   ; data_out0        ;
; |CONTROL1|control:inst|Equal0~34                                                           ; |CONTROL1|control:inst|Equal0~34                                                           ; data_out0        ;
; |CONTROL1|control:inst|i~431                                                               ; |CONTROL1|control:inst|i~431                                                               ; data_out0        ;
; |CONTROL1|control:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |CONTROL1|control:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; data_out0        ;
; |CONTROL1|control:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |CONTROL1|control:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |CONTROL1|control:inst|i~432                                                               ; |CONTROL1|control:inst|i~432                                                               ; data_out0        ;
; |CONTROL1|control:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |CONTROL1|control:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; data_out0        ;
; |CONTROL1|control:inst|i~433                                                               ; |CONTROL1|control:inst|i~433                                                               ; data_out0        ;
; |CONTROL1|control:inst|Equal2~898                                                          ; |CONTROL1|control:inst|Equal2~898                                                          ; data_out0        ;
; |CONTROL1|control:inst|Equal3~76                                                           ; |CONTROL1|control:inst|Equal3~76                                                           ; data_out0        ;
; |CONTROL1|control:inst|Selector0~12                                                        ; |CONTROL1|control:inst|Selector0~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|WideOr0                                                             ; |CONTROL1|control:inst|WideOr0                                                             ; data_out0        ;
; |CONTROL1|inst2                                                                            ; |CONTROL1|inst2                                                                            ; data_out0        ;
; |CONTROL1|control:inst|Selector1~12                                                        ; |CONTROL1|control:inst|Selector1~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|Selector2~12                                                        ; |CONTROL1|control:inst|Selector2~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|Selector3~12                                                        ; |CONTROL1|control:inst|Selector3~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|Equal4~78                                                           ; |CONTROL1|control:inst|Equal4~78                                                           ; data_out0        ;
; |CONTROL1|control:inst|Selector4~12                                                        ; |CONTROL1|control:inst|Selector4~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|WideOr1                                                             ; |CONTROL1|control:inst|WideOr1                                                             ; data_out0        ;
; |CONTROL1|control:inst|Selector5~12                                                        ; |CONTROL1|control:inst|Selector5~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|Selector6~12                                                        ; |CONTROL1|control:inst|Selector6~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|Equal5~88                                                           ; |CONTROL1|control:inst|Equal5~88                                                           ; data_out0        ;
; |CONTROL1|control:inst|Selector8~12                                                        ; |CONTROL1|control:inst|Selector8~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|WideOr2                                                             ; |CONTROL1|control:inst|WideOr2                                                             ; data_out0        ;
; |CONTROL1|control:inst|Selector9~12                                                        ; |CONTROL1|control:inst|Selector9~12                                                        ; data_out0        ;
; |CONTROL1|control:inst|Selector10~12                                                       ; |CONTROL1|control:inst|Selector10~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|Equal6~78                                                           ; |CONTROL1|control:inst|Equal6~78                                                           ; data_out0        ;
; |CONTROL1|control:inst|Selector12~12                                                       ; |CONTROL1|control:inst|Selector12~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|WideOr3                                                             ; |CONTROL1|control:inst|WideOr3                                                             ; data_out0        ;
; |CONTROL1|control:inst|Selector13~12                                                       ; |CONTROL1|control:inst|Selector13~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|Selector14~12                                                       ; |CONTROL1|control:inst|Selector14~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|Selector15~12                                                       ; |CONTROL1|control:inst|Selector15~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|Equal7~76                                                           ; |CONTROL1|control:inst|Equal7~76                                                           ; data_out0        ;
; |CONTROL1|control:inst|Selector16~12                                                       ; |CONTROL1|control:inst|Selector16~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|WideOr4                                                             ; |CONTROL1|control:inst|WideOr4                                                             ; data_out0        ;
; |CONTROL1|control:inst|Selector17~12                                                       ; |CONTROL1|control:inst|Selector17~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|Selector18~12                                                       ; |CONTROL1|control:inst|Selector18~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|Selector19~12                                                       ; |CONTROL1|control:inst|Selector19~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|WideOr5                                                             ; |CONTROL1|control:inst|WideOr5                                                             ; data_out0        ;
; |CONTROL1|control:inst|Selector22~12                                                       ; |CONTROL1|control:inst|Selector22~12                                                       ; data_out0        ;
; |CONTROL1|control:inst|i[1]                                                                ; |CONTROL1|control:inst|i[1]                                                                ; data_out0        ;
; |CONTROL1|control:inst|i[2]                                                                ; |CONTROL1|control:inst|i[2]                                                                ; data_out0        ;
; |CONTROL1|CLK                                                                              ; |CONTROL1|CLK                                                                              ; dataout          ;
; |CONTROL1|dout[2]                                                                          ; |CONTROL1|dout[2]                                                                          ; dataout          ;
; |CONTROL1|en                                                                               ; |CONTROL1|en                                                                               ; dataout          ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+