keyboard.tan.rpt

是一些很好的FPGA设计实例

; Clock Setup: 'C[3]'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; COUNT:inst|7493:inst1|15                                                            ; COUNT:inst|7493:inst1|15             ; C[3]       ; C[3]     ; 0            ;
; Clock Setup: 'C[2]'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; COUNT:inst|7493:inst1|15                                                            ; COUNT:inst|7493:inst1|15             ; C[2]       ; C[2]     ; 0            ;
; Clock Setup: 'C[1]'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; COUNT:inst|7493:inst1|15                                                            ; COUNT:inst|7493:inst1|15             ; C[1]       ; C[1]     ; 0            ;
; Clock Setup: 'C[0]'          ; N/A   ; None          ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; COUNT:inst|7493:inst1|15                                                            ; COUNT:inst|7493:inst1|15             ; C[0]       ; C[0]     ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                     ;                                      ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------------------------------------------------+--------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30QC208-2      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clk1            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; C[0]            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; C[1]            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; C[2]            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; C[3]            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                       ;
+-------+------------------------------------------------+--------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                     ; To                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 113.64 MHz ( period = 8.800 ns )               ; COUNT:inst|7493:inst1|15 ; KEYVALUE:inst1|dout[3]   ; clk        ; clk      ; None                        ; None                      ; 0.900 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; COUNT:inst|7493:inst1|16 ; KEYVALUE:inst1|dout[2]   ; clk        ; clk      ; None                        ; None                      ; 2.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 7493:inst5|15            ; 7493:inst5|14            ; clk        ; clk      ; None                        ; None                      ; 1.800 ns                ;