example.map.summary

来自「是一些很好的FPGA设计实例」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Sun Feb 11 03:10:30 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : example
Top-level Entity Name : example
Family : ACEX1K
Total logic elements : 172
Total pins : 43
Total memory bits : 0
Total PLLs : 0