example.tan.rpt

是一些很好的FPGA设计实例

; N/A           ; None        ; 0.600 ns  ; D[29] ; smdisplay:inst|74175:inst29|15 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; D[27] ; smdisplay:inst|74175:inst28|13 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; D[25] ; smdisplay:inst|74175:inst28|15 ; clk      ;
; N/A           ; None        ; -2.100 ns ; D[16] ; smdisplay:inst|74175:inst22|16 ; clk      ;
; N/A           ; None        ; -2.200 ns ; D[19] ; smdisplay:inst|74175:inst22|13 ; clk      ;
; N/A           ; None        ; -2.500 ns ; D[22] ; smdisplay:inst|74175:inst27|14 ; clk      ;
; N/A           ; None        ; -2.500 ns ; D[21] ; smdisplay:inst|74175:inst27|15 ; clk      ;
; N/A           ; None        ; -2.500 ns ; D[20] ; smdisplay:inst|74175:inst27|16 ; clk      ;
; N/A           ; None        ; -2.500 ns ; D[14] ; smdisplay:inst|74175:inst17|14 ; clk      ;
; N/A           ; None        ; -2.600 ns ; D[15] ; smdisplay:inst|74175:inst17|13 ; clk      ;
; N/A           ; None        ; -2.700 ns ; D[4]  ; smdisplay:inst|74175:inst7|16  ; clk      ;
; N/A           ; None        ; -2.700 ns ; D[0]  ; smdisplay:inst|74175:inst|16   ; clk      ;
; N/A           ; None        ; -2.700 ns ; D[7]  ; smdisplay:inst|74175:inst7|13  ; clk      ;
; N/A           ; None        ; -2.700 ns ; D[3]  ; smdisplay:inst|74175:inst|13   ; clk      ;
; N/A           ; None        ; -2.700 ns ; D[1]  ; smdisplay:inst|74175:inst|15   ; clk      ;
; N/A           ; None        ; -2.700 ns ; D[5]  ; smdisplay:inst|74175:inst7|15  ; clk      ;
; N/A           ; None        ; -2.800 ns ; D[23] ; smdisplay:inst|74175:inst27|13 ; clk      ;
; N/A           ; None        ; -2.800 ns ; D[12] ; smdisplay:inst|74175:inst17|16 ; clk      ;
; N/A           ; None        ; -3.200 ns ; D[11] ; smdisplay:inst|74175:inst12|13 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[18] ; smdisplay:inst|74175:inst22|14 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[30] ; smdisplay:inst|74175:inst29|14 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[24] ; smdisplay:inst|74175:inst28|16 ; clk      ;
; N/A           ; None        ; -3.400 ns ; D[26] ; smdisplay:inst|74175:inst28|14 ; clk      ;
; N/A           ; None        ; -3.500 ns ; D[17] ; smdisplay:inst|74175:inst22|15 ; clk      ;
; N/A           ; None        ; -3.500 ns ; D[28] ; smdisplay:inst|74175:inst29|16 ; clk      ;
; N/A           ; None        ; -3.600 ns ; D[2]  ; smdisplay:inst|74175:inst|14   ; clk      ;
; N/A           ; None        ; -3.700 ns ; D[13] ; smdisplay:inst|74175:inst17|15 ; clk      ;
; N/A           ; None        ; -3.800 ns ; D[8]  ; smdisplay:inst|74175:inst12|16 ; clk      ;
; N/A           ; None        ; -3.800 ns ; D[6]  ; smdisplay:inst|74175:inst7|14  ; clk      ;
; N/A           ; None        ; -3.900 ns ; D[10] ; smdisplay:inst|74175:inst12|14 ; clk      ;
; N/A           ; None        ; -3.900 ns ; D[9]  ; smdisplay:inst|74175:inst12|15 ; clk      ;
+---------------+-------------+-----------+-------+--------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 11 03:10:41 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off example -c example
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "7493:inst2|16" as buffer
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "7493:inst2|15" and destination register "7493:inst2|14"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E36; Fanout = 31; REG Node = '7493:inst2|15'
            Info: 2: + IC(0.200 ns) + CELL(0.800 ns) = 1.000 ns; Loc. = LC4_E36; Fanout = 9; REG Node = '7493:inst2|14'
            Info: Total cell delay = 0.800 ns ( 80.00 % )
            Info: Total interconnect delay = 0.200 ns ( 20.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 5.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 33; CLK Node = 'clk'
                Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_A28; Fanout = 70; REG Node = '7493:inst2|16'
                Info: 3: + IC(3.600 ns) + CELL(0.000 ns) = 5.800 ns; Loc. = LC4_E36; Fanout = 9; REG Node = '7493:inst2|14'
                Info: Total cell delay = 1.900 ns ( 32.76 % )
                Info: Total interconnect delay = 3.900 ns ( 67.24 % )
            Info: - Longest clock path from clock "clk" to source register is 5.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 33; CLK Node = 'clk'
                Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_A28; Fanout = 70; REG Node = '7493:inst2|16'
                Info: 3: + IC(3.600 ns) + CELL(0.000 ns) = 5.800 ns; Loc. = LC3_E36; Fanout = 31; REG Node = '7493:inst2|15'
                Info: Total cell delay = 1.900 ns ( 32.76 % )
                Info: Total interconnect delay = 3.900 ns ( 67.24 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "smdisplay:inst|74175:inst12|14" (data pin = "D[10]", clock pin = "clk") is 5.500 ns
    Info: + Longest pin to register delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_55; Fanout = 1; PIN Node = 'D[10]'
        Info: 2: + IC(2.700 ns) + CELL(0.500 ns) = 6.700 ns; Loc. = LC1_E8; Fanout = 9; REG Node = 'smdisplay:inst|74175:inst12|14'
        Info: Total cell delay = 4.000 ns ( 59.70 % )
        Info: Total interconnect delay = 2.700 ns ( 40.30 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_E8; Fanout = 9; REG Node = 'smdisplay:inst|74175:inst12|14'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: tco from clock "clk" to destination pin "OC" through register "7493:inst2|16" is 20.400 ns
    Info: + Longest clock path from clock "clk" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_A28; Fanout = 70; REG Node = '7493:inst2|16'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 18.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A28; Fanout = 70; REG Node = '7493:inst2|16'
        Info: 2: + IC(3.300 ns) + CELL(1.100 ns) = 4.400 ns; Loc. = LC1_E15; Fanout = 3; COMB Node = 'smdisplay:inst|74151:inst6|f74151:sub|70~158'
        Info: 3: + IC(1.200 ns) + CELL(1.100 ns) = 6.700 ns; Loc. = LC4_E1; Fanout = 1; COMB Node = 'smdisplay:inst|74151:inst23|f74151:sub|70~258'
        Info: 4: + IC(2.100 ns) + CELL(0.500 ns) = 9.300 ns; Loc. = LC4_E31; Fanout = 1; COMB Node = 'smdisplay:inst|74151:inst23|f74151:sub|74~10'
        Info: 5: + IC(0.000 ns) + CELL(1.200 ns) = 10.500 ns; Loc. = LC5_E31; Fanout = 1; COMB Node = 'smdisplay:inst|74151:inst23|f74151:sub|77~3'
        Info: 6: + IC(0.800 ns) + CELL(0.900 ns) = 12.200 ns; Loc. = LC2_E34; Fanout = 1; COMB Node = 'smdisplay:inst|74151:inst23|f74151:sub|81~4'
        Info: 7: + IC(1.400 ns) + CELL(4.600 ns) = 18.200 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'OC'
        Info: Total cell delay = 9.400 ns ( 51.65 % )
        Info: Total interconnect delay = 8.800 ns ( 48.35 % )
Info: th for register "smdisplay:inst|74175:inst29|13" (data pin = "D[31]", clock pin = "clk") is 0.600 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_E10; Fanout = 5; REG Node = 'smdisplay:inst|74175:inst29|13'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.000 ns
    Info: - Shortest pin to register delay is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_183; Fanout = 1; PIN Node = 'D[31]'
        Info: 2: + IC(0.200 ns) + CELL(0.500 ns) = 2.200 ns; Loc. = LC1_E10; Fanout = 5; REG Node = 'smdisplay:inst|74175:inst29|13'
        Info: Total cell delay = 2.000 ns ( 90.91 % )
        Info: Total interconnect delay = 0.200 ns ( 9.09 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Feb 11 03:10:42 2007
    Info: Elapsed time: 00:00:01