reg.tan.rpt

是一些很好的FPGA设计实例

; N/A   ; None         ; 7.200 ns   ; C    ; 74194:inst|39 ; H        ;
; N/A   ; None         ; 7.200 ns   ; B    ; 74194:inst|40 ; H        ;
; N/A   ; None         ; 7.200 ns   ; A    ; 74194:inst|41 ; H        ;
; N/A   ; None         ; 6.600 ns   ; SR   ; 74194:inst|41 ; H        ;
+-------+--------------+------------+------+---------------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+---------------+----+------------+
; Slack ; Required tco ; Actual tco ; From          ; To ; From Clock ;
+-------+--------------+------------+---------------+----+------------+
; N/A   ; None         ; 9.400 ns   ; 74194:inst|38 ; QD ; H          ;
; N/A   ; None         ; 9.400 ns   ; 74194:inst|39 ; QC ; H          ;
; N/A   ; None         ; 9.400 ns   ; 74194:inst|40 ; QB ; H          ;
; N/A   ; None         ; 9.400 ns   ; 74194:inst|41 ; QA ; H          ;
+-------+--------------+------------+---------------+----+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To            ; To Clock ;
+---------------+-------------+-----------+------+---------------+----------+
; N/A           ; None        ; -5.000 ns ; SR   ; 74194:inst|41 ; H        ;
; N/A           ; None        ; -5.400 ns ; F    ; 74194:inst|41 ; H        ;
; N/A           ; None        ; -5.400 ns ; F    ; 74194:inst|40 ; H        ;
; N/A           ; None        ; -5.400 ns ; F    ; 74194:inst|39 ; H        ;
; N/A           ; None        ; -5.400 ns ; E    ; 74194:inst|41 ; H        ;
; N/A           ; None        ; -5.400 ns ; E    ; 74194:inst|40 ; H        ;
; N/A           ; None        ; -5.400 ns ; E    ; 74194:inst|39 ; H        ;
; N/A           ; None        ; -5.600 ns ; C    ; 74194:inst|39 ; H        ;
; N/A           ; None        ; -5.600 ns ; B    ; 74194:inst|40 ; H        ;
; N/A           ; None        ; -5.600 ns ; A    ; 74194:inst|41 ; H        ;
; N/A           ; None        ; -5.900 ns ; F    ; 74194:inst|38 ; H        ;
; N/A           ; None        ; -5.900 ns ; E    ; 74194:inst|38 ; H        ;
; N/A           ; None        ; -6.500 ns ; SL   ; 74194:inst|38 ; H        ;
; N/A           ; None        ; -6.600 ns ; D    ; 74194:inst|38 ; H        ;
+---------------+-------------+-----------+------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Jan 20 01:22:32 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off REG -c REG
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "H" is an undefined clock
Info: Clock "H" Internal fmax is restricted to 200.0 MHz between source register "74194:inst|39" and destination register "74194:inst|40"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F2; Fanout = 4; REG Node = '74194:inst|39'
            Info: 2: + IC(0.700 ns) + CELL(0.700 ns) = 1.400 ns; Loc. = LC2_F1; Fanout = 1; COMB Node = '74194:inst|36~141'
            Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 2.600 ns; Loc. = LC3_F1; Fanout = 1; COMB Node = '74194:inst|36~138'
            Info: 4: + IC(0.200 ns) + CELL(0.500 ns) = 3.300 ns; Loc. = LC7_F1; Fanout = 4; REG Node = '74194:inst|40'
            Info: Total cell delay = 2.400 ns ( 72.73 % )
            Info: Total interconnect delay = 0.900 ns ( 27.27 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "H" to destination register is 1.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'H'
                Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC7_F1; Fanout = 4; REG Node = '74194:inst|40'
                Info: Total cell delay = 1.500 ns ( 83.33 % )
                Info: Total interconnect delay = 0.300 ns ( 16.67 % )
            Info: - Longest clock path from clock "H" to source register is 1.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'H'
                Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_F2; Fanout = 4; REG Node = '74194:inst|39'
                Info: Total cell delay = 1.500 ns ( 83.33 % )
                Info: Total interconnect delay = 0.300 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "74194:inst|38" (data pin = "E", clock pin = "H") is 8.400 ns
    Info: + Longest pin to register delay is 9.600 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_54; Fanout = 8; PIN Node = 'E'
        Info: 2: + IC(2.900 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC6_F3; Fanout = 1; COMB Node = '74194:inst|34~141'
        Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 8.400 ns; Loc. = LC7_F3; Fanout = 1; COMB Node = '74194:inst|34~138'
        Info: 4: + IC(0.700 ns) + CELL(0.500 ns) = 9.600 ns; Loc. = LC2_F2; Fanout = 3; REG Node = '74194:inst|38'
        Info: Total cell delay = 6.000 ns ( 62.50 % )
        Info: Total interconnect delay = 3.600 ns ( 37.50 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "H" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'H'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_F2; Fanout = 3; REG Node = '74194:inst|38'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: tco from clock "H" to destination pin "QD" through register "74194:inst|38" is 9.400 ns
    Info: + Longest clock path from clock "H" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'H'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_F2; Fanout = 3; REG Node = '74194:inst|38'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_F2; Fanout = 3; REG Node = '74194:inst|38'
        Info: 2: + IC(2.600 ns) + CELL(4.600 ns) = 7.200 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'QD'
        Info: Total cell delay = 4.600 ns ( 63.89 % )
        Info: Total interconnect delay = 2.600 ns ( 36.11 % )
Info: th for register "74194:inst|41" (data pin = "SR", clock pin = "H") is -5.000 ns
    Info: + Longest clock path from clock "H" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'H'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC4_F1; Fanout = 3; REG Node = '74194:inst|41'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.000 ns
    Info: - Shortest pin to register delay is 7.800 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_57; Fanout = 1; PIN Node = 'SR'
        Info: 2: + IC(2.700 ns) + CELL(0.900 ns) = 7.100 ns; Loc. = LC6_F1; Fanout = 1; COMB Node = '74194:inst|37~138'
        Info: 3: + IC(0.200 ns) + CELL(0.500 ns) = 7.800 ns; Loc. = LC4_F1; Fanout = 3; REG Node = '74194:inst|41'
        Info: Total cell delay = 4.900 ns ( 62.82 % )
        Info: Total interconnect delay = 2.900 ns ( 37.18 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jan 20 01:22:33 2007
    Info: Elapsed time: 00:00:01