reg_latch.hif

是一些很好的FPGA设计实例

Version 6.0 Build 178 04/27/2006 SJ Full Version
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-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
reg_latch
# storage
db|reg_latch.(0).cnf
db|reg_latch.(0).cnf
# case_insensitive
# source_file
reg_latch.bdf
13a7647c8567c25cab75899734cb17c
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# hierarchies {
|
}
# end
# entity
74175
# storage
db|reg_latch.(1).cnf
db|reg_latch.(1).cnf
# case_insensitive
# source_file
..|..|quartus60|libraries|others|maxplus2|74175.bdf
33ec197e8a955715d86a7afa0777
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# hierarchies {
74175:inst
}
# end
# complete