reg.hif

是一些很好的FPGA设计实例

Version 6.0 Build 178 04/27/2006 SJ Full Version
2
21
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
REG
# storage
db|REG.(0).cnf
db|REG.(0).cnf
# case_insensitive
# source_file
REG.bdf
19e680fb872cbcf1e4daac3743f2b195
24
# hierarchies {
|
}
# end
# entity
74194
# storage
db|REG.(1).cnf
db|REG.(1).cnf
# case_insensitive
# source_file
..|..|quartus60|libraries|others|maxplus2|74194.bdf
efddb3c18ee8b2edae5334dcb8570fe
24
# hierarchies {
74194:inst
}
# end
# complete